Abstract: Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO includes a ring of serially connected inverters, a set of bypass circuits and a set of variable delay units. The bypass circuits are coupled to the ring of serially connected inverters to bypass one or more of the serially connected inverters when enabled. Each variable delay unit delays signal transitions at the input of a corresponding one of the serially connected inverters by a variable amount. The variable delay units may be positioned in series with the ring of inverters, in parallel with the bypass paths, or in parallel with corresponding inverters in the ring of inverters.

Abstract: Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memories that have increasing data latencies and amounts of storage. In a first mode which is suitable to support a microprocessor mode of a dual-mode processor, each data access proceeds conventionally, with accesses to successively higher levels of cache memory. In a second mode which is suitable to support a DSP mode of the dual-mode processor, the memory system bypasses the lower level cache and directly accesses the higher level cache in order to achieve a fixed latency (with enough cache storage to be useful to operate the processor in a DSP mode.

Abstract: Systems and methods for performing logic built-in-self-tests (LBISTs) where data comparisons are performed in the MISR. In one embodiment, a STUMPS-type LBIST architecture includes scan chains interposed between portions of the functional logic of the logic circuit. Test bit patterns are scanned into the scan chains, propagated through the functional logic, and captured in scan chains following the functional logic. The bits are scanned out of the scan chains into a self-compare MISR that creates a signature from the computed bit patterns and then compares the signature of the computed bit patterns with an expected signature, giving a pass/fail result. This single bit result reduces the bandwidth required to communicate the result(s) of the LBIST testing to the test equipment. As a result, a larger number of devices can be tested by a given piece of test equipment.

Abstract: Systems and methods for performing logic built-in-self-tests (LBISTS) in digital circuits. In one embodiment, the operation of LBIST circuitry is suspended at the end of each test cycle so that the bit patterns generated by the functional logic of the device under test can be examined to determine if any errors occurred during the test cycle. Pseudorandom bit patterns are scanned into the scan chains interposed between portions of the functional logic circuit and then propagated through the functional logic. The resulting bit patterns are captured in scan chains following the functional logic and then scanned out of the scan chains. The bit patterns are processed and compared to corresponding data generated by a parallel LBIST system in a device that is known to operate properly. The LBIST test cycles are then halted if there are errors in the generated bit patterns or resumed if there are no errors.

Abstract: Systems and methods for enforcing in-order execution of commands sent from a master device to a slave device, where it is not necessary to provide a data buffer to store data associated with commands that are delayed to enforce in-order execution. In one embodiment, when a slave receives an execution synchronization command from a master, it determines whether its command queue contains unissued commands associated with master. If the command queue contains unissued commands, the slave issues a retry responsive to the execution synchronization command. If the command queue does not contain unissued commands, the slave issues an acknowledgment responsive to the execution synchronization command. The master will retry the execution synchronization command until the previous commands have been completed. Because the slave does not queue up any commands that would be delayed by the execution synchronization command, it does not have to provide space to store any associated data.

Abstract: Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.

Abstract: Systems and methods for providing ride-through for interruptions in the power supplied to drives that are used to control equipment such as downhole submersible pumps. In one embodiment, a variable speed drive includes converter and inverter sections, a capacitor bank and a control system. The drive shuts down the converter section upon detecting a disruption in the AC input power and continues to generate output power by drawing on the energy stored in the capacitor bank. When the AC input power returns (or begins to return) to normal, the drive resumes operation of the converter section in a controlled manner (e.g., by presetting the firing angle of the SCR's in the converter to match the voltage across the capacitor bank.) The drive thereby limits the current that recharges the capacitor bank and prevents sudden inrushes of current that could damage the drive.

Abstract: Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embodiment, an LBIST system comprises a plurality of scan latches and forcing logic coupled to a first set of the scan latches which provide inputs to selected target logic. The forcing logic is configured to overwrite values stored in the first set of scan latches with desired values. In one embodiment, the forcing logic includes a bypass path that enables shifting of unaltered bit patterns around the first set of scan latches. Bits in the bypass path may be inverted when the bypass path is not being used in order to help detect errors in the operation of the bypass path.

Abstract: Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.

Abstract: Systems and methods for coupling pipes made of dissimilar materials in applications that are subject to large variations in temperature. In one embodiment, a connection comprises a first flange made of a first material and a second flange made of a second material. Each flange is designed to be welded to a pipe of the same material. One of the flanges has a male mating surface, while the other flanges as a female mating surface. The male flange is made of the material that experiences greater expansion or less contraction when the temperature of the connection is changed from a connection temperature to an operating temperature. The female flange is made of the other material. A sealing ring having elastic properties is preferably used between the mating surfaces of the flanges.

Abstract: Systems and methods for accessing data in a memory, where a register is provided to temporarily store data from a write operation and to make the data available for read operations that are performed immediately following the write operation and are directed to the same data. In one embodiment, a memory system includes an array of a first type of memory cells and a register having cells of a second type. The second type of cells is designed to stabilize data more quickly than the first type. Data is written concurrently into the memory array and the register. When a read operation is directed to the location of an immediately preceding write operation, the data is read from the register. When a read operation is directed to a location that is not coincident with an immediately preceding write operation, the data is read from the memory array.

Abstract: Systems and methods for controlling the execution of LBIST test cycles to allow identification of errors in bit patterns produced by the functional logic of a device under test. In one embodiment, an LBIST controller enables continuous execution of LBIST test cycles (including functional and scan shift phases) prior to a test cycle in which an error arises. In the test cycle in which the error arises, the controller allows execution of the functional phase, but not the following scan shift phase. The computed bit patterns captured in the scan chains are thereby retained in the scan chains, rather than being accumulated into a single MISR signature value. The computed bit patterns can then be retrieved from the scan chains (e.g., via a JTAG chain) and examined to determine the exact location of the error.

Abstract: Systems and methods for providing illumination suitable for imaging devices such as laser projection systems, wherein the illumination pattern is adjustable by modifying one or more characteristics of a controlled angle diffuser. In one embodiment, a highly collimated (e.g., laser light) beam is passed through a holographic diffuser to create a well defined cone angle for the light emanating from each point on the diffuser. This light is focused into an illumination image that is controlled by the prescription of the diffuser. In one embodiment, the diffuser can be positioned to alternately place different regions having different prescriptions in the optical path corresponding to the illumination image. In one embodiment, the diffuser can be continually moved to eliminate speckling and “worminess” in the illumination image.

Abstract: Systems for actuating a pair of pipe flanges to cause the flanges to be sealingly engaged. In one embodiment, a connection includes a first flange, a second flange and a coupling. The first and second flanges have complementary mating surfaces. The coupling engages both the first and second flanges, with the flanges oriented so that their mating surfaces face each other. The coupling movably engages the first flange to form a cavity between the coupling and the flange. When fluid is forced into the cavity, expansion of the cavity moves the first mating surface toward the second mating surface. This is continued until the mating surfaces make contact and a desired amount of pressure is applied between them to create a seal. The pressure of the fluid is distributed evenly through the cavity, so the contact pressure between the mating surfaces of the flanges is also evenly distributed.

Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.

Abstract: Systems and methods for executing program instructions in a data processor at a variable rate. In one embodiment, a processor is configured to examine received instructions, identify an execution time associated with each instruction, and generate clock pulses at necessary intervals to obtain the appropriate execution time for each instruction. Instructions may be associated with types or “bins” that are in turn associated with corresponding execution times. The clock pulses may be generated by routing successive pulses through circuits that delay the pulses by desired amounts of time. The processor may also be configured to identify instructions which are input/output (I/O) instructions and are initiated or terminated by completion of handshake procedures and therefore have execution times that vary from one instance to the next.

Abstract: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.

Abstract: Systems and methods for generating a true 3-D display, where each of a viewer's eyes not only sees a different scene, but the scene changes continuously as the viewer moves his/her head or change his/her position from one angular location to another angular location with respect to the display screen. In one embodiment, a system comprises a set of 2-D image projectors and a display screen. The 2-D image projectors are configured to project individual 2-D images substantially in focus on the display screen. The display screen then diffuses (or reflects) each pixel from each of the 2-D images into a small angular slice. This enables the viewer observing the display screen to see a different one of the 2-D images with each eye. Further, the image seen by each eye varies as the viewer moves his or her head with respect to the display screen.

Abstract: Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

Abstract: Systems and methods for processing data using an array of data processing elements that are coupled together with a variable precision interconnect. One embodiment comprises data processing elements coupled by variable precision interconnects to form a row-column array. The interconnects and/or data processing elements may be synchronous or asynchronous. The data processing elements may operate in a fixed manner, or they may be programmable, and selectable data processing elements in the array may be bypassed. The interconnects and data processing elements may be configured to handle data in a digit-serial manner, with tags for each digit identifying whether the digit is the first and/or last digit in a data word. The data processing elements may be coupled to a system bus that enables communication of data between the data processing elements and external devices and allows control information to be communicated to and from the data processing elements.