Abstract: An operational amplifier or comparator is provided in which internal parasitic capacitances are buffered to increase the gain bandwidth product of the amplifier.

Abstract: Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.

Abstract: A charging circuit is provided to decrease the settling time of a reference capacitor storing a reference voltage for data acquisition circuits. The charging circuit includes one or more comparator circuits for comparing the voltage across the reference capacitor to the reference voltage provided by a reference source. If the voltage from the reference source deviates by a predetermined amount, one or more buffer circuits rapidly charge the reference capacitor to a voltage substantially equal to the new reference voltage. The reference source is then coupled directly to the capacitor to complete the charging of the capacitor to the new reference voltage.

Abstract: Conversion is achieved by subdividing the intergrate and deintegrate periods into a plurality of integrate and deintegrate phases. Power frequency rejection can be maintained by defining the combined integrate phases to integrate over at least one complete power line cycle. Sychronization of the integrate phases with the power line cycle is maintained by separating integrate phases with a combined deintegrate and rest phase of fixed duration.

Abstract: Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.

Abstract: An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.

Abstract: A programmable interface to selectively couple the terminals of an electronic system to desired circuit locations within the system. By applying programming signals to the input terminals of the interface in a prescribed sequence, the interface is programmed so that subsequently applied control signals will be coupled to the desired circuit locations. The function served by each terminal thus depends on the programming sequence. Reprogramming can change the function of each of the terminals by coupling them to different circuit locations.

Abstract: An improved analog to digital converter in which an approximate digital representation is provided by a parallel analog to digital converter and the conversion is completed by a successive approximation analog to digital converter.

Abstract: A current limited insulated gate transistor (IGT) is disclosed wherein the individual cells are rectangular and each has four discrete, mutually spaced emitter regions to provide a reduced gate periphery. Each cell lacks emitter portions at the cell corners to reduce current crowding in the corner areas. The size of each cell is kept small to decrease the forward voltage drop of the IGT at its operating current level and the spacing between individual cells of the IGT is minimized in order to further reduce the maximum IGT current. These features enable the cell to survive a short-circuit load condition by preventing the maximum current from reaching the latch-up level.

Abstract: An improved analog to digital converter is provided in which high and low order bytes of the digital output can be sequentially generated by a single flash converter circuit. Upon the generation of the high order byte, a high byte equivalent voltage is subtracted from the analog input voltage and the residual is multiplied by a predetermined factor. The resultant product signal is converted by the same flash converter circuit to the low order byte. In addition, the low scale and full scale of the converter inputs may be programmed to have the same polarity as, or the opposite polarity of, the polarities of the reference voltages.