Abstract: An error checking circuit that performs RS encoding and decoding operations and also generates CRC codes includes a configurable two-stage combinatorial circuit that carries out selected finite-field arithmetic operations associated with RS and CRC coding. Input registers store the generator polynomial and operand coefficients associated with the data blocks or packets being encoded or decoded, and an output register holds the intermediate working result and at the end the final result of the finite-field arithmetic operation. Each stage of the combinatorial circuit includes sets of AND and XOR gates performing bitwise finite-field multiply and add on the operand bits, and the connections between registers and gates and between gates in the two stages are configured by multiplexer units responsive to RS and CRC instructions. The two-stage combinatorial block can be replicated into a 4-stage or 8-stage arithmetic circuit for CRC mode.

Abstract: A power-on management system for an on-chip voltage down-converter, monitoring both external and internal voltage supplies to independently determine when both supplies have reached minimum levels for proper operation of on-chip circuitry. The power-on management system supplies output signals that: control the discharge of the internal supply nodes at the initiation of power-on; force the active mode of the voltage down-converter; and deactivate a fast local voltage reference on completion of power-on.

Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract: A flash memory with a page erase architecture using a local decoding scheme instead of the global decoding scheme known in the prior art. Under the local decoding scheme, the flash memory is partitioned into sections. Each section comprises a plurality of local decoder and local circuitry. The local circuitry comprises switches controlled by the global decoders and these switches switch only in erase operation and not read operation. The reading time is not affected. Each local decoder is coupled to each row of the memory array. Each local decoder comprises a PMOS transistor for passing negative voltages and two NMOS transistors for passing positive voltages so that a page erase is achieved and unselected rows can be protected from unwanted erasure without additional and complex circuitry. The global decoder is located outside of the sectors and provides global signals to all sectors via the local circuitry, thus saving area.

Abstract: The present invention allows the use of low speed USB reader/connector to be use for full speed and high-speed transmission by introducing an accurate clock element into the smart card. In addition, the present invention eliminate the need of having a clock element in any USB compatible reader/connector, making the reader/connector a much simpler device that can be manufactured in a lower cost.

Abstract: This patent describes a new method and apparatus which allows optical cavities to be used simply and effectively as absorption cells for the purpose of performing sensitive absorption spectroscopy. This method introduces a continuous-wave light beam into the cavity using an off-axis cavity alignment geometry to systematically eliminate the resonances commonly associated with optical cavities, while preserving the absorption signal amplifying properties of such cavities. This reduces the complexity of the apparatus considerably compared with other optical cavity-based absorption methods when applied in conjunction with either cavity ringdown spectroscopy or integrated cavity output spectroscopy. This method can also be used to characterize other optical loss processes occurring within the cavity such as scattering or total extinction coefficients, and to determine the losses due to the cavity mirrors themselves (reflectometry).

Abstract: A test circuit aids in accurately measuring the input pin to output pin signal propagation speed through an integrated circuit by providing a D flip-flop in the signal path near the output pad to register the arrival of a test signal transition. The flip-flop is clocked at various clock frequencies. At the high frequencies, test signal transitions applied at the input pad coincident with a clock transition having not arrived at the output pad in time to be registered at the next clock transition. At lower clock frequencies, the test transition has time to propagate through the integrated circuit and thus will be registered by the flip-flop. By successively lowering the clock frequency and sending test signals through the circuit, one-half of that clock period that just registers the test signal transition corresponds to the input-to-output delay time being measured.

Abstract: A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.

Abstract: A variable charge pump circuit uses a plurality of selectable loads to minimize the voltage ripples of the pumped output by selecting the appropriate load for a preselected pump voltage. The charge pump circuit also compares the pump voltage to a reference voltage to shut down the variable charge pump circuit if the pump voltage is larger than the reference voltage. The charge pump circuit also compares the maximum voltage output to the reference voltage to monitor whether the maximum ripple on voltage output is larger than the reference voltage. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages, a plurality of loads each associated with a specific pump voltage, and a load selector means coupled to the output pump and the plurality of loads for selecting a load associated with a specific pump voltage.

Abstract: A computer program provides fast generation and testing of probable prime numbers for cryptographic applications. The program instructions executed on computer hardware execute steps that include a smart increment program function that finds successive candidates using a table of congruent values that are relatively prime to a selected set of very small primes do identify an increment to the next candidate, thereby sieving out about ¾ths of the really obvious components that don't need to be subjected to trial division. The program instructions also include a small primes testing program function that speeds trial division against a list of small primes by carrying out the division on modular reduced values rather than the very large candidates themselves. Only the about 10% of the candidates that pass the small primes test will then be subjected to more rigorous, but time consuming, probable primality tests.

Abstract: A sense amplifier that is configurable to operate in two modes in order to control a voltage swing on the sense amplifier output. The sense amplifier has two feedback paths including a first feedback path having a transistor with a fast response time in order to allow the circuit to operate as fast as possible, and a second feedback path for providing voltage swing control. In the first operating mode, the “turbo” mode, both feedback paths are in operation to provide a higher margin of swing control, thus higher sensing speed. In the second operating mode, the “non-turbo” mode, only the first feedback path is in operation which allows for greater stability and a reduction in power consumption.

Abstract: Chemically specific fiber and waveguide sensors are formed in a fiber optic or optical waveguide material in which injected light is trapped within a Bragg grating optical cavity. The Bragg cavity effectively traps the light for long times, corresponding to effective path lengths equal to hundreds or thousands of meters in the fiber or waveguide medium. The Bragg grating optical cavity is surrounded by a cladding of chemically sensitive material whose optical properties change when exposed to specific chemicals or classes of chemicals. The change in the optical properties of the cladding results in a change in the light trapping characteristics of the fiber or waveguide. Changes in optical transmission of the fiber optic or waveguide sensor can then be related to the concentration of specific chemicals or classes of chemicals in the environment surrounding the sensor.

Abstract: A MOS transistor having utility as a charge storage device, as in a nonvolatile memory device, or as an amplifier, using the charge storage feature of the device as a way to modulate the conductivity of a channel between source and drain electrodes. Over a doped substrate, a gate oxide layer isolates a doped, electrically isolated, charge reservoir layer from the substrate. An overlying tunnel barrier layer isolates the charge reservoir layer from a nanocrystal layer capable of receiving or dispensing electric charge to the charge reservoir layer under the influence of a control gate overlying the nanocrystal layer and separated by an oxide layer. Electric charge on the charge reservoir layer influences the conductivity of the channel. The device may be operated in a memory mode, like an EEPROM, or in an amplifier mode where changes in the gate voltage are reflected in conductivity changes of the channel.

Abstract: A solid-waste conversion plant produces useful products and electrical energy in a closed system with zero emission of pollutants into the atmosphere. The plant is characterized by catalytic ionic-impact chambers having a pair of electrodes that establish an electric arc. The electric arc breaks down solid waste molecules into a plasma of atomic constituents which exothermically recombine into simple molecules upon leaving the plasma. A primary chamber converts carbon-based waste into solidifiable metal, sulfur and glassy slag extractable from the bottom of the chamber, and into gas containing CO, H2, and CH4. A second chamber contains high carbon waste input that is converted by the arc into incandescent coke, which converts CO2 and H2O in the gas from the first chamber into more CO, H2 and CH4, thereby forming a fuel gas. The fuel gas is combusted in gas turbine generators to produce electricity for operating the electric arcs, plus a sellable surplus.

Abstract: In order to establish boundary current levels for more than two memory states, a circuit is provided that uses reference currents defining the center of each state. The reference currents are defined by multiple pre-programmed reference memory cells or by a single reference memory cell together with a current mirror that sets the other reference currents at specified proportions of a first reference current. With these reference currents, an analog circuit block generates fractional currents at (1−m) and m of the reference currents, where m is a specified margin value equal to 50% for read operations and less than 50% for program verify operations, then combines fractional currents for adjacent states to produce the boundary current levels. The fractional currents may be obtained with pairs of current mirrors biased by sense amplifiers for the various reference currents.

Abstract: A two-phase step motor with bifilar winding around the stator poles is connected to phases &agr; and &bgr; (90° apart) of a two-phase driver in a manner that maximizes torque at medium speed operation and minimizes vibrations. In particular, the coils that are wound around different groups of stator poles are connected in series. In one set, both coils are connected in a forward sense around the stator, while in the other set, the two coils are connected in opposite senses. All coils are energized in every phase of a pulse cycle. The properties are intermediate between that of convention series and parallel stator coil connections.

Abstract: An apparatus for and method of determining the states on a wafer to be processed, e.g., whether residue in the form of metal is left on the surface of a wafer after chemical-mechanical polishing. The method comprises the steps of calculating first spectral signatures from a first set of measurement sites on one or more training wafers. Each measurement site is known to be in one of two or more states. In the case of only two states, the states could be “residue present” and “residue absent” states. The next step involves correlating the first spectral signatures to the states on the training wafer(s). The next step then involves calculating second spectral signatures from a second set of measurement sites on a wafer where the states are unknown. The final step is determining the states on the wafer to be processed based on the second spectral signatures.

Abstract: A telephone wiring terminal for use in an office building environment connects dedicated telephone lines and PBX or KEY telephone extensions to selected office jacks within an office building. The terminal comprises a customer programmable, electronic cross-connect device in the form of a wall mountable chassis-box with an internal non-volatile switch bank, an internal computer system controlling the switch bank, external telephone line connectors leading to and from the switch bank and external programming access to the computer system. The dedicated lines and extensions connect to one set of connectors while telephone lines leading to the jacks connect to a second set of connectors. Programming access may include a keypad and display on the front of the chassis-box, as well as com and modem ports on the chassis.

Abstract: An asymmetric waveguide pair (1440) with a differential thermal response has an optical coupling frequency that may be thermo-optically tuned. Tuning may also be accomplished by applying an electric field (1445) across a liquid crystal portion (1442) of the waveguide structure. The waveguide pair may include a grating and be used as a frequency selective coupler for an optical resonator. The differential waveguide pair may also be used as a temperature or electric field sensor, or it may be used in a waveguide array to adjust a phase relationship, e.g. in an arrayed waveguide grating.

Abstract: Tunable add-drop and cross connect devices include materials with negative refractive index dependence on temperature and temperature independent coincidence between modes of an athermal ring resonator and a set of specified frequencies, e.g. for DWDM telecommunications channels. The free spectral range may be adjusted to equal a rational fraction of the specified frequency interval. The operating frequency may be selected without substantially tuning the resonator modes by a thermo-optically tuned feedback element having a waveguide pair with differential thermal response. The operating frequency may be induced to hop digitally between the specified frequencies.