Abstract: The data processing system includes processing nodes and a graphics display device for processing a graphics data stream. The data processing system partitions a graphics data stream into a data segments or work groups for processing by the processing nodes. Next, the data segments are distributed for processing to the processing nodes. In response to receiving a data segment at a processing node, the data segment is processed to produce a processed data segment. The processed data segments are recombined into a processed graphics data stream. This processed graphics data stream is coupled to the graphics display device.

Abstract: Cathode ray tube display apparatus comprises a cathode ray tube display screen for displaying successive frames of a non-interlaced video image in response to excitation by at least one raster-scanned electron beam. A line timebase circuit sequentially addresses each electron beam to successive pixels on the screen in a line of a raster in response to a line timebase sync signal. A frame timebase circuit sequentially addresses each electron beam to successive lines of the raster in response to a frame timebase sync signal. The frame timebase circuit comprises means for offsetting successive frames of the video image in a direction transverse of the lines of the raster by a distance less than the spacing of adjacent lines of the raster. Gaps between adjacent pixels on successive lines of the raster are made invisible to the viewer because the persistence of viewer's eye effectively integrates the image content of successive frames.

Abstract: A graphic display system capable of cutting out a partial image according to the invention includes image storage means, outline drawing means for drawing an outline of the partial image to be cut out, mask data generator means for generating mask data according to the outline, and partial image write means for writing into the image storage means only a portion of the source image which is not masked by the mask data. The image storage means is an all point addressable (APA) memory in which a source image storage area for storing the source image, a work storage area for storing a dot pattern representing the outline, and a destination storage areas for storing the partial image are allocated. The mask data generator means generates mask data, whereby a region enclosed with the outline dot pattern is put in the non-masked state, while the rest is put in the masked state.

Abstract: Apparatus for setting the color point of a color display device comprises a video signal generator for generating an image on the display device and a color analyzer for measuring the chromaticity of the image to produce digital coordinates corresponding to the color point of the image on a chromaticity reference chart. The apparatus further comprises a computer system connected to the color analyzer. The computer system includes interface means for reading the digital coordinates from the color analyzer, display means for displaying a cursor at a point corresponding to the coordinates within a graphical representation of the reference chart, and processor means for moving the cursor within the graphical representation in response to a change in the coordinates read from the color analyzer. The apparatus advantageously permits rapid adjustment of the color point of a display device to a desired value with a high level of measurement repeatability.

Abstract: A programmable display controller allows reconfiguration of bit plane memory and video output connections based upon the type of display device employed. The display controller allows for the definition of multiple bit planes when the display device supports color or multiple gray shades. Simultaneous storage of images to all defined planes is accomplished through the use of multi-store logic. Multi-store logic transforms a data stream defining foreground and background portions of an image within a given display area into a form that can be simultaneously written to the bit planes as required to create the necessary output. Under processor control, a video palette may be loaded to ensure that display output signals are routed to the correct connector pins. The routing of particular signals to particular pins is reconfigured through the selection and loading of the applicable video palette.

Abstract: In a computer graphics display system, a method and processor are disclosed for drawing one of a concave polygon, self-intersecting polygon and polygon with polygonal hole. Pursuant to the method, a mask buffer organized into an M.times.N plurality of addressable constituent pixels is used. The method includes the steps of: masking the pixels of the mask buffer corresponding to the boundary of the polygon and drawing the pixels in the frame buffer of the display system corresponding to the boundary of the polygon; masking the pixels in the mask buffer corresponding to the interior of the polygon while preserving the masked pixels in the mask buffer corresponding to the polygon boundary; and drawing the pixels in the frame buffer corresponding to the interior of the polygon with reference to the masked polygon interior pixels in the mask buffer.

Abstract: An image processor has image processing logic for detecting pixel data representing stepped chrominance or luminance transitions characteristic of staircase aliasing in a source image and for producing an output image including selective antialiasing on the detected stepped transitions. The image processing logic operates as a post processor, but is able to give much better results than conventional convolution filtering.

Abstract: Apparatus and method for calibrating a display, such as a raster display, copier, liquid crystal display (LCD) or a printer is disclosed. The processor, under the control of an algorithm, generates adjustment images with a symbol that appears light on dark when misadjusted in one direction; dark on light when misadjusted the other way; and disappears at the point when the display is adjusted correctly. The invention can be used to calibrate brightness, color, gamma and sharpness.

Abstract: Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached.

Abstract: A hardware filter for controlling the detectability, highlighting and invisibility of graphics primitives. Each of the three display attributes (detectability, highlighting, and invisibility) being controlled has associated with it both an inclusion counter and an exclusion counter, for a total of six counters. Associated with each class name is a flag, indicating whether the class name is a member of the currently active set, as well as a 6-bit string indicating the effect of the class on each of the six filters. On traversal of the structure hierarchy, upon encountering an order for the addition of a class name to the set, and if the flag corresponding to the class name has not already been set, the flag is set and the corresponding filter counters are incremented in parallel by gating an incrementing signal with the 6-bit string.

Abstract: A method of generating a two-dimensional (2-D) image of a transform of a three-dimensional (3-D) solid object involves sub-dividing a 3-D box defining viewing space into sub-boxes, generating test-cells in object space by performing an inverse transform on the sub-boxes and determining which of the test-cells intersect the object. Thus, the need to transform the object itself is avoided. A particular application of the method is the generation of 2-D perspective images of a 3-D solid object. A graphics processing system including means for performing the method is defined.

Abstract: In a logic circuit having clocked state latches and combinatorial logic for functional processing of a task in response to functional clocking of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic is provided for suspending task processing by interrupting the functional clocking of the state latches and, during such suspension, scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performed by a logic circuit in a multiprocessing enviornment.

Abstract: A method and apparatus for evaluating and rendering parametric surfaces. The apparatus includes a system memory connected to a graphics control processor, which is connected to local memory, and then connected in a pipelined arrangement to a plurality of parallel floating point processors, another floating point processor, a clipping processor and a frame buffer.

Abstract: A compensating upshift circuit providing low signal degradation and operating at high speed and at low power. Capacitor shunted diodes cross-couple the collectors and bases of two transistors. The cross-coupling eliminates signal swing degradation in the upshift circuit and controls current through the two collector resistors. Equalized collector resistor current eliminates signal swing degradation while providing an upshift circuit with short delays. The capacitor shunted diodes can be replaced by diode connected transistors configured to provide the necessary collector-base capacitance.

Abstract: In a computer graphics display system, a method and processor are disclosed for drawing a `polygon with edge`-type primitive encountered in certain high level graphics interface programs. Both the method and processor use a mask buffer organized into a plurality of addressable constituent pixels, each pixel preferably being two bits deep. The method includes: masking the pixels in the mask buffer corresponding to the boundary to the polygon; drawing the pixels in the frame buffer of the display system corresponding to the boundary of the polygon; and drawing the pixels in the frame buffer corresponding to the interior of the polygon with reference to the content of the mask buffer. Corresponding processing steps for writing Z values in a depth buffer are also described. In addition, specific algorithms for implementing the method are set forth, along with an embodiment of a display processor implementing the method.

Abstract: A graphics display system picking function tracks machine states of pickable primitive operators through the use of a pick stack and machine state memory. The pick stack operates as a stack when accessed by pipeline processors. Pipeline processors can add an element to the stack or remove elements from the stack as structures are processed. Selection or picking of an object causes a graphics control processor to randomly access the pick stack to determine the attributes of a picked primitive. The machine state memory is implemented as a video RAM allowing rapid copying of rows containing machine states for various structure levels in the hierarchy. A first area of the machine state memory stores the states relating to the structures in the hierarchy as they are executed. A second area retains an abbreviated state description for each pickable primitive while a final area contains abbreviated machine state information for picked objects to be echoed by the system.

Abstract: A graphics data management system that includes control tables for quickly accessing information about the display structures to be drawn. A series of control tables and hashed indexes to graphics descriptors allow structure storage editing commands to quickly and effectively edit structure details. A hierarchical graphics data language results in a hierarchical network of structure elements and associated graphic primitive commands. The editor provides a method to preserve the hierarchy while efficiently accomplishing editing tasks. Hashing tables to the structure I.D., pick I.D., label I.D. and a chained list of execute structures are maintained to rapidly access and control those elements. Structure storage is maintained in local memory with certain portions shared with the graphics control processor.

Abstract: A table editor for editing a table of rows and columns using a pointing device and display station. The table editor stores information about the lines and boxes that make up the table. A pointing device is used to select horizontal or vertical lines or a box defined by horizontal and vertical lines for an operation. The user can select a command to insert rows or columns, to delete rows or columns, or to concatenate the contents of two or more boxes. The determination of whether rows or columns are to be acted upon is made from the orientation of the lines selected by the pointing device.

Abstract: A method and apparatus for generating image data representing an iso-valued surface. A series of points in three dimensional space each having positional data and an assigned scalar value is analyzed by dividing the space into tetrahedral elements, generating tetrahedral element representative normal vectors, generating vertex representative normal vectors data, and calculating pixel values for viewing rays passing through the tetrahedra. Tetrahedral elements have the advantage of requiring only the solution of linear equations instead of quadratic equations. The use of representative normal vector data rather than geometric data for each associated triangle greatly reduces the storage requirements for processing the data. The reduced data storage and associated reduced processing time allows generation of iso-valued surfaces at high speed with a minimum memory requirement.

Abstract: An assembly of chases is disposed on the exterior of a rack supporting discrete computer, DASD, communications, storage and similar electronic modules to provide input/output cable management, cooling passages to supply cooling air to each of the electronic units and a power distribution chase to manage the power distribution to the separate electronic modules. The cable management chase provides efficient storage of excess cable length to improve appearance and efficiency of electronic module installation.