Abstract: A method for controlling a high speed memory unit M to be read from, and written to, as initiated by clock signals of comparable speed, this method involving: providing a timing coordinator unit with bi-stable store for storing and presenting certain input signals to the memory unit in conjunction with the clock signals so as to be immediately useable thereby and so that the memory unit can responsively output data to a user stage; these input signals being arranged to include commands R/W to Read or Write, Address signals and Data signals; and the memory unit being maintained in “ready-to-read” condition at all times except during receipt of write commands.

Abstract: A memory system includes a data memory and a distinct cache status memory for storing status information regarding the data memory. A memory controller generates timing and control signals for accessing the data memory in a page mode while concurrently accessing the cache status memory in a word mode. In the preferred embodiment, the data memory is accessed in a four word per page mode while a read-modify-write operation is performed on an associated cache status memory. In order to conserve pins on the memory controller, the cache status memory shares a substantial portion of the address lines which are received by the data memory. Supplemental cache status address lines are generated by programmable control logic, which may be incorporated into the memory controller. Programmable control logic generates supplemental address lines based on the maximum number of data memory modules, the size of an addressed data memory module and the number of cache status columns.

Abstract: An arrangement for automatically, selectably diverting, different-weight checks being transported along a prescribed track with divert-blade means at a prescribed divert-station therealong, said checks comprising "standard" and "non-standard", heavier versions, this arrangement comprising, in combination with the foregoing:weight sense means, disposed along said track, upstream of said divert station, for sensing at least a mass characteristic of passing checks and outputting mass-indicating signals SS representative thereof; actuate means arranged to thrust said blade means across said track and associated actuate-adjust means for adjusting actuation-torque of said actuate means responsive to associated torque-adjust signals AA input thereto; and control means arranged to receive said mass-indicating signals SS, manipulating them and applying associated torque-adjust signals AA to said actuate-adjust means whereby to automatically adjust and control the torque applied to said blade means according to the sen

Abstract: An image-based transaction processing system which captures and stores images of debit and credit transaction documents, while also extracting document data for storage in a computer data base. The computer processes the extracted document data to identify out-of-balance transactions. The document images of an out-of-balance transaction are sent to a balancing workstation which provides a multi-window display for controllably displaying the transaction in a manner which permits the cause of the out-of-balance condition to be readily determined and corrected. The multi-window display includes windows for displaying selected images of debit and credit documents as well as windows for displaying credit and debit amounts and the out-of-balance amount of the transaction.

Abstract: A method of processing documents involving: transporting the documents at high speed unidirectionally and without pause along a prescribed transport path past at least one image-lift site; scanning the entirety of respective document faces at the sites with illumination from a light-source; providing a light-guide along a path between the light-source and the sites; providing an energy-shaping gate, disposed at each of the sites and acting to channel the imaging illumination energy there; and providing a heat-dissipation stage disposed operatively adjacent the light source and acting to extract infra-red energy therefrom and dissipate it so as to shield the sites; this heat-dissipation stage comprising an infra-red extraction unit arranged and adapted to remove a substantial part of the infra-red energy projected along a prescribed beam-path from a high-intensity spectral source; the extraction unit comprising: a selective reflector interrupting the beam path and adapted to divert infra-red energy as an infra

Abstract: Apparatus for transporting and processing documents and maintaining a preset nominal inter-document gap, g.sub.nom therebetween, this apparatus including transport stage for picking each document from an input stack and advancing it toward a destination at a controlled rate; a sensor unit for sensing the distance g between the so-moved document and the following document; and a control stage for determining the variance .gradient.g, between g.sub.nom and g, while driving each successive document along a feed path from the input stack at adjustable times; with the sensor unit inputting the control means which is adapted to responsively determine the variance-distance .gradient.g, and to thereupon control the transport stage to adjust the acceleration or deceleration of a following document and so tend to reduce this variance-distance .gradient.g.

Abstract: A method of providing a track-cleaning wand for use in a document handling machine having a track along which documents are transported past sensors separated by a distance d and recessed away from the side walls of the track, this wand including a rigid handle with, at one end, a rigid elongate spacer bar carrying a pair of like brushes spaced apart by the sensor separation-distance and having bristles long enough to reach the face of a sensor, when the spacer bar is swept along the track.

Abstract: In a system for processing and imaging documents to develop a stream of digital, video bit sets, each related to a different document is a passing array, this system including an arrangement for simultaneously compressing a number of said bit-sets for different document images and sending the results to output, this arrangement as comprising:a preprocessing stage for distributing each said bit set in a pair, of like parallel bit-compression paths, one, a Master path for half the bits in a set, the other a Slave path for the other half as controlled by The Master, with both input to a common buffer, each compression path being adapted to execute a first compression and then a conditional second compression when certain initial factors are indicated and to provide a real-time-compressed output to this buffer; andboth said compressions being performed on a single, two pass stage of a Histogram/Compressor printed circuit board.

Abstract: An I/O system where there is provided a Task Control Processor which provides for the scheduling of the different central processors for the highest priority processes to be run. When an initiate I/O operation is detected, the respective processor is released from the process that it is currently running and can be assigned to the next highest priority process. When the requested I/O operation has been completed, the Task Control Processor is signalled so that the Task Control Processor can put the requesting process back into the priority list of processes to be run by the main central processors.

Abstract: In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sup.B before reattempting such access, with each said time period T.sup.B being provided by the random number generator so as to likely differentiate from competing agents.

Abstract: In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sub.B before reattempting such access, with each said time period T.sub.B being provided by the random number generator so as to likely differentiate from competing agents.

Abstract: An adapter arrangement for internetworking a non-CTOS computer means with a network of CTOS terminals, including a system-bus, this arrangement being adapted for introduction into, and cooperation with, the non-CTOS computer and comprising CTOS-net bus means for transferring signals from the system-bus plus a communication control stage for controlling and transferring signals to/from the CTOS network and a net-interface stage.

Abstract: An electronic document-imaging arrangement which generates imaging-bits representing a given document and transfers these bits on a "per-document basis" to various successive electronic processing stages and, finally, to data base storage; this arrangement also including a tag unit adapted to create "sync-tag" bits unique for each such imaged document and transfer these tag bits, along with the imaging bits, for each document to each processing stage that handles the imaging bits on a per document basis, and finally to an associated interface for final matching and removal of the tag bits.

Abstract: A system and method for detecting errors during the storage and retrieval of file information between a file cache system and a host computer system utilizes a block check sequence key as redundant data included in each block of file data transferred. The block check sequence key is generated by key generation logic and accompanies each block of file data stored in the file cache system by the host computer system. The block check sequence key is a compressed representation of the data within the selected block, as well as unique file and block identification information supplied by the requester of the write operation. When the block is retrieved from the file cache system, the system generates a new block check sequence key based on the data within the retrieved block and the unique file and block identification information supplied by the requester of the read operation. Validation logic ensures that if the retrieved key and the newly generated key does not match, an error signal is activated.

Abstract: A data base management system operating on a first host processor in a multi-host data processing environment performs consistency checking to detect the occurrence of an error. Based on the severity of the error condition, the data base management system may optionally notify the user of the error condition, save to a file the contents of memory allocated to the data base management system, or abort the data base management system. For error conditions which require either saving the allocated memory or aborting the data base management system, a message is automatically sent to the data base management systems operating on the other host-processors in the multi-host data processing environment. Upon receipt of the message indicative of the error condition, each of the receiving data base management systems saves to a file the contents of memory allocated on the host processor on which each of the receiving data base management systems is operating.

Abstract: A self-timing clock generator for use with a precharged Static Random Access Memory (SRAM). The invention asynchronously switches the memory clock pulse to a precharge signal upon recognition of completion of a memory access cycle. Recognition of completion of the memory access cycle is performed in one of two ways. The first method monitors for the existence of a preprogrammed memory-completion bit which becomes active at the same time that read or write data becomes valid at the data outputs. The second method monitors for the existence of a memory-completion bit generated through the use of an odd parity generator. An alternate clocking method is provided to bypass the asynchronous self-timing clock generator, and to allow for synchronous clocking of the precharged SRAM. An external clocking method is also provided to directly clock the precharged SRAM.

Abstract: A method which provides for controlling the ordering of document images in an image based document processing system so as to minimize the likelihood of an operator making an incorrect entry. In a particular preferred embodiment, transactions comprised of a single deposit ticket and a single check are reordered when displayed for amount entry so that they are separated by at least one document image. This minimizes data entry errors, since an operator cannot assume that successively displayed items are related.

Abstract: A processor is disclosed having two levels of subinstructions, with the processor data bus being selectable as either a 16 bit or 32 bit wide bus under nanoprogram control.

Abstract: A fast BCD/Binary Adder in which provision is made for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate correction value conditionally subtracted from the result where required to give a proper BCD result. High speed operation is achieved by merging the binary input logic with the correction logic so as to provide for addition of the correction value concurrently with the addition of the input operands in a manner which automatically takes into account any inter-bit carries that may be produced by the correction value. In addition, provision is made for concurrently producing conditional sums (one assuming the presence of an input carry and the other assuming the absence of a carry) in parallel with the performance of look-ahead carry operations.

Abstract: The present invention provides a high-speed decoder for decoding signals encoded into Nordstrom-Robinson 16,256,6 non-linear code. The novel decoder receives a transmitted encoded signal in the form of a multi-dimensional vector to be decoded. The decoder comprises a plurality of computing elements coupled to the input encoded signals and produces modified multi-dimensional vectors and subcode values which are decoded in a plurality of subcode decoders to produce intermediate inner product values and information words associated with the intermediate inner product values. The intermediate inner product values are compared in comparator means to provide the maximum intermediate inner product value and its associated information which is indicative of the best mathematical estimate of the encoded signal being decoded.