Abstract: A method and apparatus for efficiently debugging and/or testing a rules based expert system. To provide guidance when updating a test sequence, the present invention contemplates identifying which rule sets and/or rules were exercised by the test sequence, and which were not exercised. The present invention also contemplates identifying the rule sets and/or rules that were exercised, and the percent of the rule sets/rules that were exercised. This and other information may be useful in identifying appropriate changes for the test sequence so that those rule sets and/or rules that were not exercised during the previous iteration are exercised in a subsequent iteration.

Abstract: A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.

Abstract: A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.

Abstract: An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined period of time. This may provide the instruction processor with enough time to determine if the architectural state change is valid before the architectural state change is actually written to the appropriate architectural state register.