Abstract: A system and method for emulating a target system's hardware using highly parallel software emulation. Target system hardware under the control of program instructions is emulated using parallel software activity routines. Each of the program instructions is sequentially provided to a series of the activity routines, where each activity routine is a stage of a software emulation pipeline. Each activity routine emulates a particular function designated by the particular program instruction of the target system. The information is forwarded from each of the stages of the series of activity routines to their successive stages in the series. Each stage forwards its associated information to its respective successive stage when the stage has completed its designated activity, and has recognized that its respective successive stage has completed its respective function and is ready to accept more information.

Abstract: A system and method for balancing database transaction request distribution between various hosts in a multiprocessor transaction processing system is provided. The transaction processing system includes a database and multiple host processors each coupled to at least one database transaction request unit. Database transaction requests sent from the host processors are collectively entered into a commonly-accessible load balancing queue. Each database transaction request is accompanied by a source identifier that identifies the database transaction request unit which initiated the corresponding database transaction request. The queued database transaction requests from the load balancing queue are processed by currently-available host processors, regardless of which host processor initiated the database transaction request.

Abstract: A system and method for providing speed-regulated data transmission between two synchronous systems in different clock domains. A first synchronous circuit includes a memory device, and a second synchronous circuit includes one or more data-requesting devices. The first synchronous circuit operates at a greater clock speed than the clock speed of the second synchronous circuit. A read request buffer queues read request signals from the data-requesting devices, and outputs one of the read request signals to the memory device. A pulse generator receives the read request signal which was output from the queue, and generates a plurality of signal pulses in response thereto. Each of the pulses occurs at a different predetermined time from the occurrence of the read request signal. One of the pulses is selected to be the read acknowledge signal, and assertion of the read acknowledge signal allows the read request buffer queue to output another read request signal.

Abstract: A system and method for providing high speed emulation of a computer system by transforming selected target instructions and bypassing target instruction decoding for those target instructions which have been transformed. A target computer system, controlled by a plurality of target instructions, is emulated on an emulation host computing system. Target instructions are successively loaded into the emulation host computing system in the order that the target instructions would be executed. The target instructions are decoded to identify the functions designated by the target instructions, and these functions are executed by the emulation host computing system. Emulation information is assigned to selected target instructions, where the emulation information controls execution of these selected target instructions, referred to as transformed instructions.

Abstract: A system and method for expediting database queries by using random sampling. Data associated with a database attribute is partitioned into multiple data classes using a query language grouping command. Each of the data classes is randomly sampled on an individual basis to obtain a corresponding number of class data samples, each of which are stored in a separate sample database table. Database queries are then applied to each of the class data samples in the sample database table.

Abstract: A system and method for monitoring and collecting performance characteristics of a target system and providing the results by way of time-division multiplexing is provided. The performance monitor includes a mechanism for latching a plurality of performance attribute signals. An output circuit, coupled to the latching mechanism, is used to output the latched performance attribute signals in groups, wherein each of the groups is a subset of all of the performance attribute signals. The performance monitor further includes a time division circuit coupled to the output circuit, to allow the output circuit to output each of the groups of performance attribute signals at different times. Each group of performance attribute signals can therefore be transmitted via common output access points, although at different times as the groups are transmitted in succession.

Abstract: A system and method for transmitting commands from one or more input/output devices to a memory is provided. An identification tag is appended to each command to define the command as either a read or write command. The read commands are separated from the write commands based on the state of the identification tag, and the read and write commands are separately queued. The read commands are stored in a first command queue, and the write commands are stored in a second, separate, command queue. The read commands in the first command queue are successively transferred to the memory upon completion of the current memory read function, and the write commands in the second command queue are successively transferred to the memory upon completion of the current memory write function. The transfer of the read and write commands is independent.

Abstract: A system and method for detecting timing design errors in a design having multiple state devices clocked by multiple clock signals. The design includes at least first and second state devices clocked by first and second clock signals. A reference time is designated, and a time differential between successive triggering edges of the first and second clock signals is calculated. The time of the occurrence of each triggering edge of the first and second clock signal is calculated with respect to the reference time, rather than directly with respect to each other. The calculation of the time differential includes storing a period time and a time offset the first and second clock signals. The time offsets are time durations measured from the reference time to the first pulse of each of the first and second clock signals that occur simultaneously with, or subsequent to, the reference time.