Abstract: Disclosed are a method and system for transferring data objects from a server to a client in a distributed computing system. The disclosed method comprises the steps of: receiving, at the server, a request from the client for the data object; determining whether a cached copy of the requested object retained by the client is the same as a current version of the requested object retained by the server, wherein the cached copy and the current version are stored in a compressed form; and transmitting the current version of the requested object from the server to the client in the compressed form if the cached copy of the requested object is not the same as the current version of the requested object.

Abstract: Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility.

Abstract: A system and method are disclosed for providing computers, particularly the Unisys A series computers, with the capability to function with disk drives of more than one sector format, especially if a predetermined sector format is inefficient and/or cost prohibitive. Interfacing is provided for processing I/O requests between a predetermined logical sector format (e.g., 180 byte sectors) and a variable physical sector format (e.g., 512 or 720 byte sectors). Read operations compare read request addresses to physical sector boundaries and discard unwanted data. Write operations, using at least one sector buffer, perform a read/modify/write cycle, such that the necessary physical sector data not associated with the write request is read into the sector buffer, modified and written back to the disk along with the write data inserted at the appropriate location. This system and method can effectively increase the usable capacity of selected disk drives by 15-20%.

Abstract: Disclosed is a telephony messaging transfer system permitting a messaging host to redistribute its processing and/or storage load to another messaging host. An administrator can dynamically control the amount of time needed to transfer specified mailboxes by monitoring the progress on-line and increasing or decreasing the number of transfer dialogs to be used in the transfer process. Also provided is a predictive simulator for simulating the transfer process and providing statistics that can be used to adjust the timing of the actual transfer.

Abstract: A technique for accepting test vectors in one format, generally proven to operate correctly, from an IC tester such as the Logic Master XL2 ("off-bench tester") and processing/converting them into another format for use in a stimulus generator such as the HFS 9009 for bench top testing. The process, which in the exemplary embodiment is implemented in software, accepts various parameters as inputs (e.g., channel name(s) for stimulus generator, range of vectors, etc.) for purposes of extraction and translation. The process provides an Interface and Initialization Unit (IIU) and a Translator Unit (TU). The IIU provides a user interface necessary for a user to select the various options available. In addition, the IIU coordinates the use of memory, file I/O and communication with the active files on the off-bench tester. The IIU verifies user selections and does error checking. Once complete, the TU translates the selected signals for the vector range entered by the user.

Abstract: A dynamic memory refresh apparatus includes a programmable refresh interval generator that generates an interval for generating a refresh request signal. The refresh interval time is based on the manufacturer specified DRAM cycle time, the system clock period, and the number of memory segments on the memory board that are supported by the computer system. The refresh interval time substantially maximizes the time between refreshes of a particular DRAM module. The dynamic refresh apparatus also includes a memory segment pointer generator that generates a memory segment pointer. The memory segment pointer points to the next memory segment to be refreshed. The memory segment pointer is generated such that the memory segments are selected in a staggered manner. In addition, the dynamic memory refresh apparatus includes a refresh request generator that generates a refresh request signal for the memory segment pointed to by the memory segment pointer.

Abstract: In a spread spectrum multipoint-to-point communication system there is provided a novel frequency to phase converter, for automatically synchronizing the PN codes of the user transmitters/receiver with the receiver/transmitter in the central hub. The highly accurate frequency to phase converter generates a highly accurate phase error signal for synchronizing the multiuser network. The frequency to phase converter includes a serial adder and a series to parallel converter and a shift register which integrates the highly accurate phase error signal values and produces a highly accurate frequency value which is applied to the input of the resident processor in the central hub transmitter/receiver. The central hub transmitter/receiver calculates the clock offset for synchronizing each of the user receiver transmitters and generates a clock adjusting signal which is transmitted to the user receiver/transmitters.

Abstract: In a high speed main frame computer system, a high speed instruction processor is provided with a high speed cache memory. The cache memory is provided with a plurality of associated memories including a tag memory. Every time the instruction processor attempts to access the cache memory, a cache set address is generated which accesses the associated memories to provide most recently used (MRU) block information, validity information and degrade block information. The accessed information is applied as inputs to a cache logic system. The cache logic system logically modifies the information to generate an update of the MRU information and writes the modified MRU information into the MRU associated memory at the set address without control or supervision on the part of the instruction processor. The cache logic system also generates the least recently used (LRU) block coded information using the MRU information, validity information and degraded block information for cache block replacement.

Abstract: Apparatus and method for coordinating cache coherency between host cache memories in a distributed information system in a system which comprises at least one main storage memory coupled to a plurality of host computers through controllers. Each host computer includes a host cache controller which maintains the state of the data stored in its associated memory and maintains communicating with a main memory controller for participating in the control of coordinated reading and writing of data between the host cache memories and the main storage memory. The system maintains cache coherency by the exchange of commands between the main memory controller and the hosts cache controllers each of which define the state of the blocks of data stored in the host cache memories.

Abstract: A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.

Abstract: A method is provided for collecting information located within a plurality of hardware elements of a computer system. The hardware elements of the plurality of hardware elements are simultaneously instructed to collect the information. The information within the instructed hardware elements is simultaneously collected. A maintenance system is provided for monitoring the computer system and determining a computer system error in accordance with the monitoring. The step of simultaneously instructing the hardware elements to collect the information is performed in accordance with a computer error determined in this manner. The hardware elements, which may be hardware processors, are provided with individual hardware modules which receive the simultaneous instructions to collect data and direct the simultaneous collection of information within the hardware elements. A transmission link is coupled to each hardware element in the computer system for transmitting the collected information.

Abstract: A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between the microprocessor and Network Interface Unit. The Network Interface Unit is memory mapped into the microprocessor's address space. Two memory mapped cache lines are used to write commands to the Network Interface Unit's Write Window and another two cache lines are used to read results of the commands from the Network Interface Unit's Read Window. The Write Window is a three port register file. Data is written into one write port and read simultaneously from two read ports. One read port is used during read operations to the Write Window while the other is used during command execution to move data to the Internal Structures block. The Read Window is a 2-1 multiplexor that is 128 bits wide.