Abstract: A method for using linear functions with counter modules for efficient implementation in PALs (Programmable Array Logic), or FPGAs (Field Programmable Gate Arrays) which generate digital control signals to a targeted digital device.An input setting pulsed digital signal A is upcounted and then is reduced by a downcounted feedback pulsed digital signal to produce a difference digital signal which involves adding an intercept value. The difference signal is multiplied by a slope-sensitivity parameter, each time expanding the numeric range and scope of the output digital control signal to the target digital device.