Abstract: An optoelectronic package with direct free space optical communication between pairs of optical transmitters and receivers located on different substrate surfaces in a closely spaced stack of chip carrying substrates is disclosed. The transmitters and receivers are aligned so that a light beam from each transmitter follows an optical path toward its respective receiver. In the stack of substrates, the transmitters and receivers are mounted on the surfaces of the substrates, many of which are separated by intervening substrates. These intervening substrates have vias, holes or transparent regions, or other optical means, at locations along the optical paths connecting the transmitters and receivers. Lenses or other concentrating means, where required, are adjacent to a transmitter so that its diverging light is focused on the intended receiver. Substrates are aligned so that the light from transmitters shines through the optical means in intervening substrates to the receivers.

Abstract: A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.

Abstract: A technique is disclosed for multiple sensor tracking which distributes data association and filtering processing among multiple processing entities but coordinates the track estimates such that track states and covariances represent the equivalent of a centralized estimate. The object of the invention is to establish and maintain a single system track for a single aircraft in a distributed processing environment. This is achieved through communication of track information among processing entities which process a single sensor's inputs. Continued updating and re-broadcasting of process data are performed between the multiple sensor's processing entities.

Abstract: A system and method of providing a temperature compensated line termination for a high speed communications bus meeting military standards specifications. A temperature compensating device exhibiting a negative temperature coefficient of resistance is connected between a power supply and the communications bus drives. In a preferred embodiment, a P-N junction in series with a Schottky diode is placed between a 3.3 volt supply and the communications bus drive modules.

Abstract: A data processor is disclosed which enables the selective simultaneous or asynchronous execution of mutually independent instructions of different classes in parallel coupled execution units and which enables the sequential execution of mutually dependent instructions of different classes by delaying the execution of a dependent instruction in a second execution unit until the completion of execution of a precursor instruction in a first execution unit. The instructions are dispatched to respective ones of a plurality of parallel coupled execution units, in accordance with their instruction class.

Abstract: A BiCMOS NAND circuit is disclosed employing low threshold n-channel FET transistors in conjunction with standard threshold n-channel FET transistors and standard threshold p-channel FET transistors. Circuit performance is maintained as the circuit devices are scaled to physically smaller FET devices and reduced power supply voltage. Furthermore, the circuit is interface compatible with standard CMOS circuits.

Abstract: The invention discloses a single competitor arbitration code for determining if only one communications module is contending for a communication data bus and gives that module access within two bus clock cycles. An aggregate code is generated by using the true and complement of the module ID. A check code for each bit is determined by adding the aggregate code for the bit and its adjacent bit. If the check code contains any zeros, then more than one module is contending for the bus. The 10-bit single arbitration scheme allows for error detection and correction on a 32-bit data bus.

Abstract: A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing transistor which effectively decouples the circuit when the circuit is not powered. The input/output interface of the cold spares have a high impedance and do not corrupt an interconnected electronic bus. The final drive transistors are reverse biased or clamped to zero to prevent any leakage paths.

Abstract: Switching of three phase wye power can be efficiently completed without synchronization between two or more energy sources. The absence of synchronism can be overcome by switching one source off and then in a very short time frame restoring the power from the second power source. The duration of the outage can be controlled and minimized so that the load never loses energy long enough to cause an operational problem. The interruption time period in this description is limited to about 100 microsecond span; long enough to avoid interaction between the separate power sources, yet short enough to be transparent to the load. Electrical transfer of loads between power sources may be controlled precisely if the switching is accomplished using solid state electronic devices. Electronic switching is more reliable and does not generate the arcs during transfers that shorten the life span of mechanical contactors.

Abstract: A vectorial neutral is provided in a delta power source. The neutral voltage point is provided by auto-transformers which correct and maintain a near constant voltage in the presence of load or bias currents. With a centered referenced voltage established, full wave rectification of a delta power source is possible.

Abstract: The improved gate drive circuit provides a continuous gate current whenever there is sufficient anode-to-cathode voltage difference across the SCR. This approach described herein eliminates the need to monitor and reapply SCR gate current after each commutation due to load current distortions. Previous SCR gate driver designs used a pulse train of gate currents to provide a means of keeping the SCRs turned on. The pulsed gate control approach has gaps in the SCR's operation and requires significant circuitry that dissipates much more drive energy. Energy for this improved driver circuit is derived from the SCR anode-to-cathode voltage differential. This eliminates the need for individual power supplies to provide isolated gate signals for each SCR. This self-powering feature reduces the intricacy of controlling multiple SCRs in multi-phase or unreferenced power systems. Flexibility provided by this method allows high power SCRs to be directly interfaced to a digital processor-type controller.

Abstract: A fused, redundancy selection circuit is disclosed which is disabled by the absence of a chip select signal. The circuit has the feature of avoiding the use of nodes with a floating potential and in this manner it provides an enhanced radiation hardened characteristic. The circuit is effectively disabled if no redundancy is required on a particular memory chip, by leaving fuses which are a part of the circuit, intact. Alternately, if the memory chip is tested to have defects, the redundancy circuit is selectively enabled to provide the desired redundancy for the chip, by blowing fuses which are a part of the circuit. Thereafter, the redundancy circuit is now an active part of the memory chip and it is selectively enabled when the chip select signal is applied to the chip. An advantageous feature of the circuit is that it does not dissipate power when its function is not required either because its enabling fuses have not been blown or alternately when the chip select signal is off.

Abstract: An improved memory array having row address inputs connected to a row address decoder and column address inputs connected to a column address decoder, the row address decoder and column address decoder having an address bus connected thereto, the memory being organized into an array of word lines organized into rows and columns having a pair of bit lines for each column, the improvement comprising, segmenting the array into a plurality of segments, each segment containing a portion of all of the bit lines; a bit equalization circuit for each segment, to equalize the potential on each bit line in the bit line pair when activated; an equalization circuit control means, having an input coupled to the input address lines, and an output connected to each equalization circuit on each respective segment of the array, for enabling the equalization circuits on those segments of the array which are not selected by the input address and for disabling the equalization circuits on that segment of the array which is select

Abstract: The current peak detector can be described as four separate sections. The first section is power distribution. The second is the analog section where the Idd current transient peak is first detected. There are two analog sections, one for Idd internal, and another for Idd external. The third section is the automatic multiplexer that controls which of the two analog sections will drive the digital section. The fourth and final section is the digital section where a voltage that is analogous to the peak current is converted to a DC voltage level with infinite memory. The digital section performs the logic function of replacing any prior digitized voltage peak with any higher voltage peak that may occur during the test period.

Abstract: In processing a priority queue, the elements are kept in an unsorted stack and are searched for the next highest priority element only after the highest priority element has been read from the holding register. Each time a new element is written into the queue, a comparison is made of the priority of the new element with the priority of the existing element in the holding register. If the new element has a higher priority, then the existing element in the holding register is written onto the top of the stack. Alternately, if the element in the holding register has the higher priority, then the new element is written onto the top of the stack. This assures that the holding register always contains the element having the highest priority. Therefore, a read of the priority queue by reading the contents of the holding register guarantees that the highest priority element is there and it can be accessed immediately without further searching the queue.

Abstract: An electrical power connector for PC boards or bus bars having low insertion force and low voltage drop across the connector. The connector features a female receptacle having a double set of opposing rows of multipoint spring contacts mating with a two-tiered male plug. The spring contacts make electrical contact to the tiers of the male plug.