Abstract: An integrated circuit modeling system facilitates automatic design of register based hardware devices by generating major pieces of the development outputs from a single input, such as a single register specification source file. The modeling code is kept coherent for all major phases of design and testing. The register specification source file contains all the register information about the device being developed. For example, each register defined in the file contains information about its offset (within its register space), access permissions, size, and field specifications. The system uses a series of associated pre-stored modeling templates in different programming languages, that access the register specification source file and automatically generate behavioral model register code and IC simulation code.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: An automatic volume control system and method for use in a multimedia computer system having at least one speaker and at least one audio generating device accumulates a status of the audio generating device to determine if it is on or off. The system recognizes an audio mute event notification signal from a notification device, such as an incoming telephone call notification signal, and selectively generates a control signal for use in varying the volume to the at least one speaker in response to the detection of the notification signal to selectively control audio from the audio generating device. The system also accommodates multiple audio generating devices. The system analyzes the location of the telephone, speakers and audio generating devices to determine the type of action that is necessary.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: A method and apparatus for reconfiguring an integrated circuit based on testing results is accomplished by an integrated circuit that includes a first circuit, a second circuit, and configuration circuitry deposited on a single die. After testing of the die, the configuration circuitry configures the integrated circuit based on the results of the testing. If both circuits passed the testing, the configuration circuitry couples, where appropriate, the first and second circuits together. If, however, the first circuit failed the testing and the second circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the second circuit were present on the die. If, however, the second circuit failed the testing and the first circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the first circuit were present on the die.

Abstract: A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Abstract: Encryption frequently needs to be used in communication networks which span different geographical regions which can be considered to be trusted to different extents. According to one embodiment, the invention uses both a strong encryption algorithm and a weak encryption algorithm. A device in the high-trusted region can encrypt using the strong algorithm and can decrypt using either the strong or weak algorithm. A device in the low-trusted region can decrypt with either the strong or the weak algorithm but can encrypt only with the weak algorithm.

Abstract: A method of encrypting or decrypting an input message block of binary data of predetermined length 2n into an output message block by dividing the message block into two equal size halves, performing one or more transformation rounds on the message block halves, each transformation round further comprising the steps of determining a key, processing the first half data block using a hash function to obtain a modified first half data block of length n, and combining the modified first half data block with the second half data block to obtain a modified second half data block of length n; and, lastly, appending the first modified half data block to the second modified half data block to obtain the output message block.

Abstract: Initializing and configuring computer hardware with firmware stored in compressed form in nonvolatile semiconductor memory. Upon startup of the computer hardware, decompression software decompress the firmware, which is then stored in another memory. The computer hardware may be an adapter board (e.g., a graphics board connected to PCI bus), the nonvolatile semiconductor memory may be physically located on the adapter board, and the firmware may be firmware for initializing and configuring the adapter board. The decompression software may be stored in the same nonvolatile semiconductor memory as the firmware, and may be written in a machine-independent language (e.g., a Forth-based language). The compression technique used may include both run-length encoding and pattern compression, and may operate at the bit level.

Abstract: A dental instrument sharpening system includes an instrument arm for holding a chiral bladed dental instrument and for facilitating movement of at least one of the chiral blades of the dental instrument to a rotatable sharpening stone. A positioning mechanism, coupled to the instrument arm, positions at least one of the chiral blades of the dental instrument in a desired predetermined position. The positioning mechanism includes a clamping mechanism and indexed slotted member. The indexed slotted member has index protrusions, such as protruding nubs, that matingly engage with indentations in the handle of the dental instrument. The handle of the dental instrument includes at least one index indentation such as a conical indentation. The index indentation and the corresponding index protrusion mate to properly position the blade of the dental instrument in a predetermined longitudinal and axial position in the clamping mechanism.