Abstract: An electronic circuit controls a non-linear electromechanical valve in order that the temperature of approximately 25 gallons of coolant water within a reservoir may be maintained within +2.8.degree. C. to -0.0.degree. C. of a set point temperature from 35.degree. F. to 100.degree. F. The valve regulates circulation of such coolant within a secondary cooling loop incorporating a non-linear heat exchanger for thermal exchange with building water flowing from 20 to 30 gallons per minute. The reservoir coolant water is subject to an essentially instantaneously variable thermal load of 0 to 20 kilowatts due to circulation through logic modules in a primary coolant loop. The electromechanical valve control circuit receives an external set point temperature signal, and a reservoir coolant temperature signal which is offset in conversion from degrees Kelvin to degrees Centigrade.

Abstract: Disclosed is an electrically operated linear actuator which is modular in design such that each module provides a component of force required to cause translational motion to a load via a linear shaft. The actuator is designed so that all modules of the actuator are utilized to provide a maximum force for initial movement of the shaft, whereas only the last module is utilized to provide a minimum force when the shaft has completed most of its translational motion. Intermediate modules between the first and last modules provide components of force for translating the shaft that vary in a uniformly ascending order from the minimum to the maximum forces.

Abstract: A novel interleaver-de-interleaver is provided which is adapted to store bits of a data stream after being error encoded. The data bits are stored in a random access memory in addresses identifiable by an array of columns and rows. The interleaver comprises address pointer means and logic for reading the data bits out of the memory addresses in a predetermined reordered sequence to provide a quasi-random pattern sequence of data bits which when transmitted are substantially immune to periodic bursts of radio frequency interference signals.

Abstract: This invention provides a novel high-gain stabilized converter circuit which is adapted to convert emitter coupled logic (ECL) signals for use in gallium arsenide (Ga As) circuits. The novel converter is adapted to be made in gallium arsenide logic on the same chip as the logic circuitry which it is driving. The converter includes a novel differential amplifier having a level shifting network at the active input and a second level shifting network at the reference input to provide a stabilized high-gain circuit which is compensated for variations in temperature and process deviations.

Abstract: A method of fabricating a "hybrid" multilayer printed circuit board combining two dissimilar plastic layers of polyimide resin/glass and of epoxy resin/glass laminates. The finished hybrid multilayer printed circuit board is for, e.g., the support of and electrical interconnection to a plurality of magnetizable memory cores. The method includes sandwiching a plurality of epoxy-glass printed circuit boards having the desired copper patterns on both sides between two polyimide-glass printed circuit boards, each having the desired copper pattern on only one side. All the printed circuit boards are laminated with epoxy-glass prepreg to form a single hybrid multilayer printed circuit board consisting of the sandwiched epoxy-glass printed circuit boards and the sandwiching polyimide-glass printed circuit boards. Interconnections between patterned layers are formed by copper-plate throughholes.

Abstract: A method and apparatus whereby an auxiliary yoke is used in conjunction with a CRT display to correctively deflect the electron beam to a true position within each pixel of a graphics figure, as the graphics figure is displayed on the CRT's screen. The apparatus thus increasing the display's resolution within each pixel so as to permit the smoothing of the displayed graphics figures.The improved resolution being achieved via a four bit binary position correction code, three bits of which are stored in the image memory at those memory addresses corresponding to the coordinates of the pixels that comprise the graphics figure, and one bit of which position correction code is stored at the immediately preceeding memory addresses. The entire position correction code in turn being decoded as the image memory is read and used to drive one or the other of the x and y coil pairs of the x-y auxiliary yoke.

Abstract: The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the central processing unit is employed to generate a plurality of phase related new clock signals. Logic circuit means are provided to sequentially attempt to employ each of the new clock signals until one of the new clock signals synchronizes with the external asynchronous signal. The logic circuit means include circuits for selecting a new clock signal to be employed by the timing circuits of the central processing unit so that the new clock is synchronized with the external asynchronous signal.

Abstract: Apparatus for and method of searching a data base using variable search criteria. The data base consists of a set of files or portions thereof. Each file is divided into a number of records whereby all records of a given file have the same format but the records of different files may have different formats. A field format register is used to define the format of the records within a given file. The field format register specifies the location and width of each field within a record. To perform a search, a field-by-field comparison of each record is made to a reference word. The comparison yields a less than, equal to or greater than result for each field of each record. A field comparison register describes the expected result of the field-by-field comparison. A given field is designated true if the comparison yields the expected result specified for that field in the field comparison register.

Abstract: Any number N of light emitting diode (LED) push-button indicator-switches are connected by one wire each to a corresponding N interconnected assemblages of four cross-coupled logical elements each. A pushbutton activated signal input through a one connective wire causes a cross-coupled flip-flop storage action within the associated assemblage which will maintain the L.E.D. lit by outputting on the selfsame connective wire after the pushbutton is released. A one-shot circuit merged in each assemblage clears via the interconnect the stored signals of all other assemblages when a new pushbutton signal is activated. One of N selections between N indicator switches is thusly obtained with only one wire connection to each.

Abstract: A memory accessing system for reading or writing consecutive addressable words is described for use in a set associative memory system. Two high speed buffer memories store words read in blocks from a slower main memory. One buffer stores even addressed words and the other stores odd addressed words. Each buffer memory has a tag memory associated with it for indicating data words stored in the buffer memories. A comparison circuit compares two addresses to be accessed to the tags and provides hit or miss signals for each address indicating residency or non-residency in the buffers. If both addressed words are resident, access to read or write the two consecutive data words is accomplished simultaneously. If either or both addressed words are not resident in the buffers, the main memory is accessed to acquire a block or blocks containing the missing addressed word or words. Consecutively addressed data words can occur within a block or across block boundary.

Abstract: Logic circuit hardware is provided for dividing a binary fraction divisor into a smaller binary fraction dividend to provide a binary fraction quotient.Initially, the divisor is stored in a storage register with its sign in the highest order bit position and remains unchanged during the division operation. Initially, the dividend is stored in a dividend shift register and is shifted left one bit before being applied to a parallel adder to perform a partial divide operation. A clock signal is provided to time the division operations, wherein, the stored dividend is added to the stored divisor in a parallel binary adder. When the highest order or sign bit of the adder is positive, the sum of the dividend and the divisor are stored in the dividend register and a binary one is stored in a quotient register. When the highest order or sign bit of the adder is negative, the dividend register is shifted left and a binary zero is filled in the quotient register.

Abstract: A tri-level serial data stream and its inverted form are received and separated into data and clock for use with standard bi-level logic. The incoming tri-level signal and its inverted form are separately biased to permit a true differential comparison and signal detection. High common mode rejection of noise that is developed between a transmitter and receiver is thus provided.

Abstract: A system for overlapping macro instruction execution is described for use in a data processing system. A pair of control storage devices each store the micro instruction sets required to execute all macro instructions in the repertoire and are used for alternate macro instructions. Each of the controlled storage devices is addressable to entry addresses by the macro instructions. After entry, addressing is by the contents of the micro instructions with provision made for conditional branching. An overlap count storage device is provided for storing overlap counts for all possible sequences of macro instructions. These overlap counts define the number of micro instructions of the current macro instruction that must be executed before the next macro instruction can proceed. Micro instruction execution is by clock cycle and are counted as they are executed. The count is compared to the stored overlap count for the current sequence of macro instructions and overlap execution is enabled when comparison is found.

Abstract: Speech compaction/replay apparatus for real time monitoring speech and filtering out periods of relative slence from a recording of the speech. The recording also containing synchronization and time code information for ensuring that on replay and in terms of real time the audio output will essentially replicates the analog speech input. The apparatus and technique minimizing the amount of storage media required to store the speech.

Abstract: A microprogrammed control system capable of overlapping the fetch and execution of microinstructions even when a conditional jump microinstruction is being executed. The control system comprises a pipeline register for storing the microinstruction currently being executed. The system also includes address circuitry for forming an "ordinary address" which is one greater than the address of the microinstruction in the pipeline register and for forming at least one "jump address" of a microinstruction occurring elsewhere in the program. A conditional jump microinstruction identifies a jump address for the microinstruction to be executed next, which jump address is only valid after the condition identified by the conditional jump instruction is tested and indicates that the jump address is to be used. Otherwise, the next microinstruction has an ordinary address.

Abstract: A non-dissipative battery charging circuit utilizing pulse width modulated constant current charging signals and having unregulated charging voltage stepped down by the use of a switching transistor and series inductor is described. Charging current is sensed and fed back to cause control of the charging cycle. Battery voltage is sensed and compared to a reference level for terminating charging when the battery is determined to be fully charged. A clocking and control system responsive to the feedback signals and the sensed voltage levels is described for controlling the activation and duration of application of charging current signals.

Abstract: A ground-to-air, voiced alerting system whereby a ground controller can communicate traffic warning messages to a pilot in an automatic fashion via a voice radio band and a voiced message generator. The system generally comprising means for transmitting a frequency shift key (FSK) encoded message to the pilot via the voice band and receiver means for decoding the same message. The decoding means, in turn, generally comprising means for identifying specific aircraft and additional means for decoding the message and producing the voiced message over the pilot's head set.

Abstract: Digital data is arranged into records for high density recording on a moving magnetic tape or other magnetic medium. A preamble and a postamble are formatted around a variable length data block to form a record for recording onto a movable magnetic medium. A unique character having a mirror image the same as the character is formatted after the preamble and before the postamble in order to allow recognition of the data when read in either forward or reverse direction. A flux change signal is always recorded in a ninth cell position of each character of the preamble, the postamble, the data and all other characters to be recorded, except in the ninth cell position of the unique character to insure a maximum of nine cell positions between successive clock signals and to permit immediate recognition of the end of a data block upon reading the unique character.

Abstract: A characteristic adder for use in a data processing system that performs floating-point arithmetic operations is described. A 1's complement subtractive adder is shown for forming the sum or difference of a pair of exponents under control of function control circuitry, along with an indication of which characteristic is larger for selecting which mantissa operand should be shifted for proper alignment. The function control circuitry responds to function signals to select addition or subtraction, provide the magnitude or complement of the results, and select between two available floating-point formats. Characteristic Overflow and Underflow is tested and signaled for each of the two possible floating-point formats.

Abstract: A combination dual wheel castor and jack combination assembly is disclosed. The assembly comprises a support structure having a nut-like portion and elongated portions attached to the nut-like portion. The elongated portions extend from the nut-like portion in opposite directions. The support structure includes a hole passing through at least one of the elongated portions and the nut-like portion. The hole is internally threaded along at least a portion of its length. A jack means comprising an elongated threaded shaft portion and a foot portion rotatably mounted to one end of said shaft portion is adapted to be threaded into the hole in the support structure. By gripping and turning the nut-like portion of the support structure, the shaft portion of the jack means is caused to move relative to the support structure in one direction or the other. A castor portion of the assembly comprises a pair of wheels which are spaced apart and attached to a swivel frame by an axle.