Abstract: In a networked computer system that includes multiple nodes and multiple networks interconnecting the nodes, a database query optimizer takes network choice into consideration when optimizing a query. The query optimizer logs historical information for queries that includes network information. A network monitor determines network characteristics of the multiple networks. The query optimizer then selects a network for a query based on the network characteristics, and optionally based on the historical information as well. The result is a query optimizer that takes network choice into consideration, thereby providing a query that is optimized according to the characteristics of the networks.

Abstract: A hosting partition update mechanism allows updating the I/O capability of a logically-partitioned computer system in a way that minimally affects the performance and availability of I/O in the computer system. When an update is needed, a new hosting partition is created with the desired update(s). The I/O adapters in the current hosting partition are then migrated to the new hosting partition. The migration of an I/O adapter from the current hosting partition to the new hosting partition is relatively fast, thereby minimally impacting system performance and availability of I/O. Once all of the I/O adapters have been migrated to the new hosting partition, the current hosting partition may be kept as a backup, or may be eliminated. Providing a new or backup hosting partition allows updates to be performed in the new or backup hosting partition in a non-disruptive manner while the current hosting partition continues to service I/O requests.

Abstract: A run-time monitor allows defining sets of run-time error criteria and corresponding diagnostic action to take when the run-time error criteria is satisfied. One way to define the run-time error criteria is to take a baseline measurement of run-time errors that occur during normal processing conditions. A run-time error criteria may then be defined that is based on the baseline measurement. In this manner, a rate of run-time errors that normally occur may be ignored, while a rate of run-time errors in excess of the run-time error criteria could automatically initiate diagnostic action. In this manner, the ability of a programmer to debug run-time errors is significantly enhanced.

Abstract: Database indexes include multiple fields that are used to track how the components of the index are used. An index component monitoring mechanism tracks how the components of the index are used, and updates fields in the index accordingly. Such component-level statistics allow a query optimizer to make more intelligent decisions regarding when to build a new index and when to discard an index, and also provide information regarding which queries are using the index, the maintenance cost of the index, and the selectivity of the index when used to process a query.

Abstract: A label on an electronic product may be written electronically and maintains the last display state when power is removed from the label. There are many different types of digital paper and electronic paper known in the art that would be suitable for use as such labels. The label includes multiple defined regions that may be independently written, with one of the regions defined to display failure information for the electronic product. In one implementation, the failure information is available on the electronic product itself. In another implementation, the failure information includes information received from a source external to the electronic product. The display of failure information on the label may be in human-readable and/or machine-readable form. The result is a label on an electronic product that provides reliable information regarding a failure of the electronic product.

Abstract: An I/O adapter sharing mechanism in a logically partitioned computer system allows sharing a network I/O adapter between logical partitions in an efficient manner. A first logical partition owns (or controls) the I/O adapter, and a second logical partition desires to use (or share) the I/O adapter. An I/O adapter device driver that includes a hardware interface is provided in the first logical partition. A virtual device driver is provided in the second logical partition that provides a set of functions that is at least partially defined by querying the I/O adapter device driver in the first logical partition. The I/O adapter sharing mechanism includes a transfer mechanism that allows data to be transferred directly from the virtual device driver in the second logical partition to the I/O adapter without passing through the I/O adapter device driver in the first logical partition.

Abstract: A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data has arrived. Instead, it keeps track of how many packets have been sent and which packets correspond to the end of a message, marking them off when acknowledge messages are received. If packets are lost, the invention determines which packet were lost, backs up to the lost packet, re-fetches the data and resends it. Embodiments of the present invention eliminate the need to queue packets, reducing silicon size and allowing the available bandwidth of the output bus to be more fully utilized.

Abstract: A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to the next. A bit value for a second thread of execution is stored in the primary latch, then transferred to the secondary latch. The bit value for a first thread of execution is then written to the primary latch. When a context switch is needed (when the first thread stalls and the second thread needs to begin execution), the register file bit can perform a context switch from the first thread to the second thread in a single clock cycle. The register file bit contains a backup latch inside the register file itself so that minimal extra wire paths are needed to or from the existing register file.

Abstract: A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data has arrived. Instead, it keeps track of how many packets have been sent and which packets correspond to the end of a message, marking them off when acknowledge messages are received. If packets are lost, the invention determines which packet were lost, backs up to the lost packet, re-fetches the data and resends it. Embodiments of the present invention eliminate the need to queue packets, reducing silicon size and allowing the available bandwidth of the output bus to be more fully utilized.

Abstract: A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.

Abstract: An apparatus and method enable batch processing of database updates without modifying generated code, i.e., without redeployment of the application server or application. A batch mechanism intercepts calls from the generated code, compiles updates into batches, and processes the updates to the database in batches. In this manner the batch mechanism takes advantage of the batch processing capabilities of the database without modifying the generated code.

Abstract: A high-frequency compound instruction mechanism and method allows performing a common compare immediate function before an add function has completed, thereby reducing the number of cycles to perform the add-compare function. By increasing the speed of performing the add-compare function, a branch mispredict signal may be provided to an instruction pipeline before data registers are affected by the pipelined instructions. The compound instruction mechanism of the preferred embodiments may be implemented within space that is primarily unused within arithmetic logic units, resulting in an implementation that only marginally increases space requirements on an integrated circuit.

Abstract: An apparatus and method use the built-in authentication and authorization functions of a directory service to perform authentication and authorization for resources that are external to the directory service. A Lightweight Directory Access Protocol (LDAP) service is used in the preferred embodiments. The LDAP directory includes built-in functions for authenticating a user that requests access to an entry. Each resource that needs to be protected is mapped to an entry in the LDAP directory. These entries that correspond to protected resources external to the LDAP directory are called proxy entries. Proxy entries contain the authorization information for the corresponding protected resource in the form of an access control list for each entry that specifies the authorized users of the entry.

Abstract: An apparatus and method inhibit multiple submission requests by placing an intermediate web page between the page where the user submits information and the following page. After a preset period of time viewing the intermediate page, the user is redirected automatically to the following page. If a user then presses “Reload” or “Refresh” on their browser, the submission of information is not duplicated, thereby hindering multiple submission requests.

Abstract: A great toe implant for replacement of a portion of the proximal phalanx has a substantially reniform bearing surface, providing a recess on the lower edge for receiving the flexor hallucis longus tendon once implanted. Retaining portions (such as small spikes) provided on the rear face of the implant engage the proximal phalanx, preventing rotation of the implant with respect to the proximal phalanx once the implant is surgically implanted. In addition, holes are provided on the lower edge of the implant to attach the implant to the flexor hallucis brevis tendons and to the proximal phalanx.