Abstract: An apparatus measures residual stress in a sample under test by measuring the penetration of an indenter on a unprocessed sample under test, and after processing of the sample under test, measuring again the penetration of the indenter on the processed sample under test, and deriving from the two penetration measurements the residual stress in a sample under test. The apparatus and method of the preferred embodiments are especially useful in determining residual stress in a printed wiring board. In this manner a direct measurement of residual stress is possible without destroying the printed wiring board.

Abstract: A watch signature for a debug watch mechanism indicates one or more allowable events, which represent allowable accesses to a watched variable. The allowed accesses implicitly include thread information by limiting the allowable operations to a single thread that first performs an allowed operation. Any operations on the watched variable that are caused by a different thread, and any operations that are caused by the same thread other than those specified in the watch signature will create a notification that an unauthorized operation on the watched variable has occurred. The debug watch mechanism of the present invention thus does not notify the user for expected operations on the variable, but provides notification for other events that do not fall within the anticipated behavior of the computer program as specified by the watch signature.

Abstract: Methods for testing interconnections on an electronic assembly include the steps of dynamically generating an interconnect topology model from one system, generating test patterns to test the interconnections, applying the test patterns to the boundary scan cells of the system under test to test the interconnections, and determining whether the interconnections match the interconnect topology model. The invention thus dynamically generates an interconnect topology model from a known working system, rather than deriving the interconnect topology model from design data that describes all the interconnections on an electronic assembly.