Abstract: A graphical system for executing a process or for programming a computer to execute the process is based on graphical programming techniques. Techniques include composing a graphical front panel of an instrument which provides a means for the user to provide input and monitor outputs of the process, composing a data flow diagram using graphical representations of data flow structures, and in response to the data flow diagram and the panel diagram, composing a sequence of execution instructions to carry out the diagrammed process in response to inputs provided by the panel to supply outputs displayed by the panel. The system is based on libraries of executable functions and variable types having corrresponding icons. The user selects icons which have corresponding entries in the libraries to assemble the diagrams.

Abstract: An integrated circuit package having a plurality of pins and a plurality of output structures connected, respectively, to the plurality of pins. Each output structure selectively provides any one of four signals including a registered signal, non-inverted or inverted, or a non-registered signal, non-inverted or inverted, to a pin. Each output structure is configurable or field-programmable by a user or purchaser of the package to provide it with any desired combination of registered and non-registered outputs.

Abstract: In an ADPCM (Adaptive Differential PCM) system, in which the signal is commonly coded in C.sub.i, Q.sub.n, and .sigma. parameters, a lower sampling rate which normally causes distortion is made possible by deriving additional parameters A.sub.k, B.sub.k as a function of the error (distortion) between the original signal S.sub.n and the sampled signal Y.sub.n. The A.sub.k, B.sub.k coefficients control a distortion filter at the receiver.

Abstract: A folding-type A/D converter for converting an analog input signal to an n-bit digital code, the A/D converter having a transfer function dividing the analog input signal into at least n-1 segments, each such n-1 segment having an amplitude level corresponding to the significance of a given bit of the digital code and having linear parts which are mirror images of one another extending over 2.sup.n transition levels L. The A/D converter includes voltage-current converters for converting voltage input signals to current signals, a plurality of circuit stages for producing the linear parts in the current domain in response to the current signals, and a converter for converting the linear parts to a logic 1 or logic 0 of the bits of the digital code.

Abstract: A memory circuit for storing data words including a core memory having a matrix of rows and columns of core cells which store bits of the data words, a row address decoder circuit for driving the rows, and a control signal generator, operative over one reset period and one recovery period, for controlling the columns and the row address decoder circuit to simultaneously charge the contents of the entire core memory to one data state.

Abstract: A phase detector for detecting in real time the difference in phase between frequency pulse signals and data pulse signals, including a control signal generator for generating control signals corresponding to the occurrence of the frequency pulse signals and the occurrence or non-occurrence of the data pulse signals, and a circuit, operative during the occurrence or non-occurrence of the data pulse signals, for producing a phase error signal indicating differences between the real time occurrence of the frequency pulse signals and the data pulse signals. Another circuit of the phase detector, if needed, responds to the control signals to correct the integral of the phase error signal.

Abstract: An MOS sampling comparator circuit including a differential amplifier for producing first and second amplified signals, a first positive feedback circuit for further amplifying the first amplified signal, a second positive feedback circuit for further amplifying the second amplified signal, a strobed latch, having a positive feedback circuit, for further amplifying and storing the signals from the first and second positive feedback circuits, and a circuit for outputting complementary logic signals in response to the latched signals. By providing the first and second positive feedback circuits, small analog differential voltage input signals to the differential amplifier are further amplified and coupled without delay to the latch, resulting in an accurate conversion of the analog input signals to logic signals at high speed.

Abstract: A circuit (10) and method for converting a circuit input frequency signal (f.sub.i) to a circuit output frequency signal (f.sub.o) comprising a phase-locked loop (22) for multiplying the input frequency signal (f.sub.i) by a value M to produce a multiple frequency signal (f.sub.i M), and a presettable divider for dividing the frequency signal (f.sub.i M) by a settable value N to produce the output frequency signal (f.sub.o). The circuit (10) and method are used to determine engine speed by converting the signal (f.sub.i) to the signal (f.sub.o) which can be used with a counter having a one second time base to determine such speed. The conversion occurs in the frequency domain and follows smoothly any change in engine speed.