Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.

Abstract: A method and apparatus for a self-correcting bandwidth request/grant protocol in a broadband wireless communication system is disclosed. The self-correcting bandwidth request/grant protocol utilizes a combination of incremental and aggregate bandwidth requests. In accordance with the present inventive protocol, CPEs primarily transmit incremental bandwidth requests to their associated base stations, followed by periodic transmissions of aggregate bandwidth requests. The use of incremental bandwidth requests reduces risks that a base station erroneously issues duplicate bandwidth allocations to the same CPE for the same connection. Race conditions that may have occurred using only aggregate bandwidth requests are eliminated by requiring the CPEs to request bandwidth in an incremental manner. However, use of periodic aggregate bandwidth requests (that express the current state of their respective connection queues) allows the present bandwidth allocation method and apparatus to be “self-correcting”.

Abstract: The present invention is a novel method and apparatus for efficiently transporting and synchronizing data between the Media Access Control (MAC) and physical communication protocol layers in a wireless communication system. An inventive method and apparatus for transporting and synchronizing to fixed-length ATM cell boundaries and for protecting against the potential misinsertion of ATM cells has been described. An inventive ATM packet format is described. The ATM packet format is used by the present invention for the transportation and synchronization of ATM cells. The ATM packets include fields that are used to detect errors occurring within each ATM cell. ATM cells are transported in exactly two TC/PHY packets, or TDUs. ATM header information is contained in the first TDU only. No ATM header information is carried by the second TDU. An entire ATM cell is discarded if an uncorrectable error is detected in the first TDU. If no uncorrectable error occurs in the first TDU, the second TDU is checked for errors.

Abstract: The present invention is a novel method and apparatus for efficiently coding and decoding data in a data transmission system. A concatenated coding scheme is presented that is easily implemented, and that provides acceptable coding performance characteristics for use in data transmission systems. The inventive concatenated channel coding technique is well suited for small or variable size packet data transmission systems. The technique may also be adapted for use in a continuous mode data transmission system. The method and apparatus reduces the complexity, cost, size, power consumption typically associated with the prior art channel coding methods and apparatuses, while still achieving acceptable coding performance. The present invention advantageously performs concatenated channel coding without the necessity of a symbol interleaver. In addition, the present invention is simple to implement and thereby consumes much less space and power that do the prior art approaches.

Abstract: A novel dynamic DFF method and apparatus using CMOS is disclosed. The present invention does not use ratioed logic transistors in implementing a first stage of the DFF design. Thus, PMOS and NMOS transistors, used in the first stage of the DFF circuit, do not have severely disproportionate P-to-N transistor size ratios. These transistors therefore can have a transistor size ratio that increases the circuit's operating speeds.

Abstract: The present invention is a method and apparatus for reducing co-channel interference. The present invention includes a powerful means for eliminating co-channel interference from base stations in a wireless communication system. The present co-channel interference reducing method and apparatus utilizes frame synchronization between selected time frames (e.g., odd and even time frames) to reduce co-channel interference. Advantageously, the present invention reduces co-channel interference and, thus, allows robust modulation schemes to operate even at worst case line-of-sight (LoS) interference scenarios of 100%. The present invention can also use an uplink/downlink ratio formula to further improve system capacity (i.e., reduce co-channel interference) in ATDD systems. The present inventive method and apparatus can be used in any type of frame based and frame synchronized communication system.

Abstract: A novel mismatched-shaping DAC architecture is described. The inventive DAC partially spectrally shapes data conversion errors. In accordance with the present invention, the DAC mismatch-shaping function is fully effective for input signal amplitude levels that are relatively low (i.e., close to mid-scale), however, the mismatch-shaping function is not fully effective for input signal amplitude levels that are relatively high. This results in the simplification in complexity, reduced power dissipation, and shortened propagation delays associated with the mismatch-shaping DAC digital logic circuitry. Exemplary delta-sigma ADC and DAC architectures adapted for use with the present inventive partial mismatch-shaping DAC are also described.

Abstract: An integrated circuit capacitor includes a silicon-on-insulator (SOI) substrate and a doped epitaxial layer of a first conductivity type formed on the SOI substrate. The doped epitaxial layer is used as a first plate of the integrated circuit capacitor. A gate oxide layer is formed on the doped epitaxial layer and is used as a dielectric layer of the integrated circuit capacitor. A polysilicon gate is formed on the gate oxide layer and is used as a second plate of the integrated circuit capacitor.

Abstract: A simple, scalable cross-degeneration circuit topology is described. The inventive cross-degeneration method and apparatus provides a circuit design having substantially improved linearity as compared to traditional circuit designs having similar power consumption. The improvement in linearity is achieved without unduly increasing circuit noise and without substantially reducing circuit bandwidth. Using the present inventive method and apparatus, a fixed circuit configuration can be used to accommodate a continuous range of specifications simply by varying component values, in contrast to the prior art requirements of providing additional devices or modifying device wiring. The inventive topology can be implemented using bipolar technologies and conventional MOS processes operating above threshold. Additionally, the inventive circuits can be implemented using other three-terminal (or multi-terminal) amplifying device technologies.

Abstract: A complex frequency shift keyed homodyned diplexed radar system and method that can accurately determine the range of one or more targets where the targets have little or no velocity relative to the radar system. The system and method generates a FSK electromagnetic wave that is reflected off the one or more targets and converted into a delayed or phase shifted baseband signal and undelayed baseband signal where the delayed and an undelayed baseband signal may be analyzed to determine the range of the one or more targets.

Abstract: A novel trench isolated guard ring region for providing RF isolation is disclosed. The semiconductor integrated circuit (IC) device of the present invention comprises a substrate, an insulating layer formed on the substrate, a buried layer formed on the insulating layer, and an epitaxial layer of a first conductivity type formed on the buried layer. A first isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds a first selected surface area of the epitaxial layer. A second isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench. A plurality of isolation chambers is formed within the first and second isolation trenches. A collector is implanted into the epitaxial layer in the guard ring region.

Abstract: An apparatus for receiving signals includes a low noise amplifier (LNA) configured to receive a radio frequency (RF) signal. An I/Q direct down converter is coupled to the LNA. The I/Q direct down converter is configured to split the RF signal into real and imaginary components and to down convert the real and imaginary components directly to baseband signals. A local oscillator (LO) is coupled to the I/Q direct down converter and is configured to drive the I/Q direct down converter. First and second filters are coupled to the I/Q direct down converter. The first and second filters are configured to filter the down converted real and imaginary components, respectively. First and second analog-to-digital converters (ADCs) are coupled to the first and second filters, respectively. The first and second ADCs are configured to convert the real and imaginary components into digital signals.

Abstract: A number of methods to display interlaced video on non-interlaced monitor are disclosed. One method is to display all of the incoming fields but one at a time, and correcting for the positional offset of one field relative to another in the interlaced data. An important aspect of the present invention is the correction of the positional offset of the two interlaced video fields. There are two ways presented to deal with the vertical offset of the two fields in accordance with the present invention. The first way is that the two fields can be displayed at different positions on the display using a non-interlaced display. The second way is that the video data can be altered to correct the positional offset between the fields. Another method of the present invention is to lock the frame rate of the output video to the incoming field rate or a multiple of the incoming field rate, or to certain sub-multiples of the incoming field rate.

Abstract: A semiconductor integrated circuit (IC) device includes a substrate, an insulating layer formed on the substrate, a buried layer formed on the insulating layer, and an epitaxial layer of a first conductivity type formed on the buried layer. A first isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds a first selected surface area of the epitaxial layer. A second isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench. A collector is implanted into the epitaxial layer in the guard ring region. A contact is made to the collector, and a conductor connects the contact to a ground node.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.

Abstract: A method and apparatus for calibrating range in a radar system. Due mainly to temperature changes in a radar system which cause frequency deviation error, range errors can be introduced into the radar system, thus adversely affecting the determination of the position of targets relative to the host platform. These range errors can be corrected by detecting and accurately estimating the frequency deviation error of a radar system. The present invention improves target position determination performance in a radar system by reducing errors introduced by the frequency deviation error. The present invention relies upon the observation that the Doppler range rate is largely unaffected by frequency deviation error, and thus, is approximately equal to the actual range rate. In accordance with a first range calibration technique of the present invention, the radar system measures the range, Doppler range rate, and azimuth angle of a target during at least two successive time instances.

Abstract: An integrated circuit inductor structure that includes a shielding pattern that induces a plurality of small eddy currents to shield the magnetic energy generated by the inductor from the substrate of the IC. The IC inductor structure is formed on a Silicon on Insulator (SOI) substrate where the substrate of the SOI has high resistivity. The shielding pattern forms a checkerboard pattern that includes a plurality of conducting regions completely isolated from each other by oxide material. The inductor has a high quality factor and a high self-resonance frequency due to the effective shielding of electromagnetic energy from the substrate of the IC while not reducing the effective inductance of the inductor.

Abstract: The present invention is a novel method and apparatus for implementing a high-precision timer utilizing a non-optimal oscillator and a high-speed oscillator wherein only one oscillator is enabled at a given moment in time. The high-precision timer method and apparatus comprises a timer and an error-correction technique. In one embodiment, the timer of the present invention is constructed from a high-speed oscillator and a low-speed non-optimal oscillator. The timer operates from the high-speed oscillator during on-the-air modes of operation and from the low-speed non-optimal oscillator during sleep modes of operation. The present inventive method corrects errors that are introduced by the non-optimal oscillator and a swallow counter. The errors are corrected using an error-correction technique having two steps: an error-determination step and an error-correction step.

Abstract: A crystal oscillator apparatus is described that has a wide dynamic frequency range and that is capable of supporting a broad range of crystal types. The present invention reduces the unwanted side effects that are associated with the prior art crystal oscillator designs, such as the clipping of signals, the introduction of signal distortion and unwanted signal harmonics. The present invention reduces the total wasted loop gain of the oscillator while also reducing the amount of integrated circuit real estate required to implement the crystal oscillator. The crystal oscillator apparatus of the present invention preferably comprises a crystal resonator circuit, an inverting amplifier, a bias circuit, a reference circuit, and a peak detector circuit. The present invention takes advantage of Automatic Gain Control (AGC) design techniques. The gain of the present crystal oscillator is automatically regulated using a closed loop circuit design.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.