Abstract: The present invention is a novel method and apparatus for implementing a high-precision timer utilizing a non-optimal oscillator and a high-speed oscillator wherein only one oscillator is enabled at a given moment in time. The high-precision timer method and apparatus comprises a timer and an error-correction technique. In one embodiment, the timer of the present invention is constructed from a high-speed oscillator and a low-speed non-optimal oscillator. The timer operates from the high-speed oscillator during on-the-air modes of operation and from the low-speed non-optimal oscillator during sleep modes of operation. The present inventive method corrects errors that are introduced by the non-optimal oscillator and a swallow counter. The errors are corrected using an error-correction technique having two steps: an error-determination step and an error-correction step.

Abstract: A crystal oscillator apparatus is described that has a wide dynamic frequency range and that is capable of supporting a broad range of crystal types. The present invention reduces the unwanted side effects that are associated with the prior art crystal oscillator designs, such as the clipping of signals, the introduction of signal distortion and unwanted signal harmonics. The present invention reduces the total wasted loop gain of the oscillator while also reducing the amount of integrated circuit real estate required to implement the crystal oscillator. The crystal oscillator apparatus of the present invention preferably comprises a crystal resonator circuit, an inverting amplifier, a bias circuit, a reference circuit, and a peak detector circuit. The present invention takes advantage of Automatic Gain Control (AGC) design techniques. The gain of the present crystal oscillator is automatically regulated using a closed loop circuit design.

Abstract: A method and apparatus for fully integrating a Voltage Controlled Oscillator (VCO) on an integrated circuit. The VCO is implemented using a differential-mode circuit design. The differential-mode implementation of the VCO preferably comprises a differential mode LC-resonator circuit, a digital capacitor, a differential pair amplifier, and a current source. The LC-resonator circuit includes at least one tuning varactor and two high Q inductors. The tuning varactor preferably has a wide tuning capacitance range. The tuning varactor is only used to “fine-tune” the center output frequency f0 of the VCO. The center output frequency f0 is coarsely tuned by the digital capacitor. The VCO high Q inductors comprise high gain, high self-resonance, and low loss IC inductors. The IC VCO is fabricated on a high resistivity substrate material using a trench isolated guard ring.

Abstract: A heterodyned double side band diplex radar system determines the range of targets as a function of the amplitude variation of reflected target Doppler signals. The present invention includes a real radar system that accurately determines the range of fading targets and the magnitude of the velocity of the targets. The present invention also includes a complex radar system that determines the relative velocity of targets in addition to the range of targets. In either embodiment, the transmitted signal may be modulated with a pseudo-random number (“PN”) sequence to attenuate or decorrelate signals reflected from targets beyond some maximum range. The modulation of the pseudo-random sequence may also attenuate or decorrelate signals reflected from targets closer than some minimum range. The present invention also includes a real radar system having BPSK modulation with PN coding. The selection of BPSK modulation enables or facilitates the implementation of a portion of the system in digital form.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.

Abstract: Integrated circuit varactor structures that include either an P-gate/N-well or N-gate/P-well layer configuration formed on an SOI substrate. The varactor structure is completely electrically isolated from the substrate of the IC by an oxide layer of the SOI substrate and by oxide-filled trenches formed on both sides of the varactor structures. The isolation trenches preferably extend to the oxide layer of the SOI substrate. The P-gate/N-well varactor structure includes N+ implant regions formed in an N-well implant layer of the varactor. The N+ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the N-well layer where the P-gate is formed over the LOCOS layer. The P-gate may be formed of polysilicon. The N-gate/P-well varactor structure includes P+ implant regions formed in a P-well implant layer of the varactor. The P+ implant regions comprise the source and the drain of a varactor.

Abstract: An efficient request-reply protocol for a client-server communication and data processing model. Under the novel protocol, a client sends a Request to a server and awaits a Reply. If the Reply is not sent before expiration of a timeout period in the client, the client sends a second Request. The server provides a conditional Acknowledge if a second Request is received from the client. Thereafter, the client waits for the server to transmit a Reply without the client sending additional Requests. Under normal conditions, the inventive protocol performs as well as the best prior art protocol (the optimistic model), while under abnormal conditions, the inventive protocol performs better than the optimistic protocol and only slightly worse than the prior art pessimistic protocol. Since normal conditions should prevail for a substantially longer amount of time than abnormal conditions, the present invention provides better average performance than either prior art client-server protocol.

Abstract: A method and apparatus for analyzing each microinstruction in a microinstruction-based electronic circuit having a plurality of registers to determine which registers in a processing cycle are not involved in the processing cycle, and preventing those registers from being clocked during such processing cycle. Hence, inactive registers during a processing cycle do not consume power at the level of active registers, thus lowering overall power usage by any system employing such gated-clock registers.

Abstract: An efficient method and apparatus for determining, recording, and analyzing the phase history of a Line-in signal. The Line-in signal is coupled to a conventional demodulator. I and Q components are output by the conventional demodulator and coupled to an IQ quantizer. The IQ quantizer determines a quadrant on an I/Q plot from the amplitude of each component. A histogram is generated which indicates in which quadrant the Line-in signal was for a first sample, and in which quadrant the Line-in signal was for a second sample, the second sample having been taken immediately after the first sample. From this histogram, the number of times the Line-in signal transitions from one quadrant to another over a predetermined period of time is known.

Abstract: A method and apparatus for digitally phase modulating and frequency upconverting communication signals to an intermediate frequency, producing the IF output with only digital hardware and without the use of digital to analog converters, analog multipliers (mixers) or power combiners. A digital phase modulator provides an in-phase and a quadrature output, each of which is coupled to one input of a relatively simple multi-bit to single-bit delta-sigma data converter. The output from the converter is a pair of single-bit digital output signals. Each such single-bit output is inverted and both the inverted single-bit output and the non-inverted single-bit output of both the in-phase and the quadrature outputs are coupled to a 4:1 multiplexer. One of these four inputs is then selected by a modulo-4 counter. The modulo-4 counter is incremented at a rate that is selected based upon the desired IF frequency.

Abstract: A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates.

Abstract: A circuit for processing related signal components, such as in-phase and quadrature signal components generated within a modulator, in which a first filter and a second filter are matched such that the gain of each such filter is nearly identical. A modulator is provided having matched filters in accordance with the present invention in which the gain "K" of each filter is equal to 1. By using a filter which has a gain of 1, the gain is removed from consideration when attempting to match the filter response of one filter to another. Furthermore, each filter is relatively simple to implement, having only four resistors, two capacitors, and two operational amplifiers.

Abstract: The present invention provides a system and methods for coding and decoding digital data to improve the subjective quality of a voice signal. According to the invention, a sampled voice waveform is compressed by an ADPCM algorithm resulting in a sequence of samples. The sequence of samples are formed into an array and coded into parity bits. Row and column checksums are preferably performed on the parity bits to form row and column vectors. The samples and row and column vectors are transmitted to a receiving unit preferably having a diversity capability. The receiver processes each diversity block by generating row and column vectors from the received samples and comparing the generated row and column vectors to the row and column vectors received. Then based on the comparison, the samples of the best diversity block are used to reconstruct the voice waveform on a sample-by-sample basis.

Abstract: A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates.

Abstract: A programmable digital modulator and methods of modulating digital data for transmission by a communication system according to operating parameters selected for various applications are provided. A two-chip system is utilized by a preferred embodiment of the invention. One chip comprises a PROM for storing impulse response data which would result from filtering the data to be transmitted. The second chip comprises a data interface for accepting input data, an address generator for generating an address of the PROM where the impulse response data is stored which corresponds to the data input to the chip and for causing the PROM to output the impulse response data stored at the address generated, and a data modulator for modulating a carrier signal with the impulse response data provided by the PROM.

Abstract: A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates.

Abstract: A method and apparatus used in the context of a digital cellular communication network for allowing a remote unit to determine the conditions under which a handoff should occur and the procedure to be followed. The method and apparatus of the present invention controls handoffs in a manner which causes the boundaries of a cell within a digital cellular network to remain relatively well defined and to very closely conform to the boundaries of a cell of an advanced mobile phone system with which the cellular digital packet data system is associated. The present invention also reduces the effort required by a remote unit within a cellular digital packet data communication system when attempting to change channels. Primary and Secondary Thresholds are defined in accordance with the present invention.

Abstract: An analog circuit for multiplying a first input signal with a second input signal. The inventive analog circuit is capable of linear operation with a low voltage power source. A first pair of transistors is coupled as a first differential pair, and a second pair of transistors is coupled as a second differential pair. The first differential pair is coupled to the second differential pair in a manner that is similar to the corrections made between a first and second differential pair of a conventional Gilbert mixer. However, the emitter degeneration resistors of the present invention are not coupled to the collectors of a third differential pair, as is the case in conventional Gilbert mixers. Rather, the degeneration resistors of the present invention are coupled directly to the negative power supply terminal.

Abstract: Methods and apparatus for improving the perceived quality of ADPCM encoded signals by magnitude limiting samples of the ADPCM encoded signals prior to the decoding of samples of the ADPCM encoded signals, preferably, a sample of the ADPCM encoded signal is magnitude limited only if a receive error is detected for the sample.

Abstract: Methods and apparatus for frequency synthesization are shown for generating an output signal of desired frequency. The frequency synthesizer includes an oscillator for generating an output signal at the desired frequency in response to a control signal. A first detector compares the output signal to a reference signal and generates a first difference signal representative of the differences, preferably in phase and frequency, between the output and the reference signals. A second detector compares the output signal to the reference signal and generates a second difference signal. A controller generates the control signal in response to either the first or second difference signal. A selector member selects between the first and second detectors to provide either the first or second control signal to the controller in response to a selection signal.