Abstract: A method and system for improving data migration from source data stripes to destination stripes in a Redundant Array of Independent Drives (RAID) logical drive migration (LDM). The invention describes a procedure for checkpointing data migrations, so that if the system should fail in the middle of the LDM, the computer can resume the LDM from the last checkpointed destination stripes, thus ensuring accurate tracking of data location. Further, the invention also provides the capability of properly checkpointing a data write to a stripe according to whether or not the stripe unit has been migrated previously.

Abstract: A method for associating a password with a secured public/private key pair is disclosed. A user public/private key pair is first established for a user. The user public/private key pair includes a user public key and a user private key. Then, the user public/private key pair is encrypted along with a random password, utilizing a chip public key. Next, a first password is generated by hashing a pass phrase. Finally, the random password is encrypted along with the first password, also utilizing the chip public key. As a result, a user can assess the user private key to perform an authentication function by providing the pass phrase.

Abstract: A cache for use in a memory controller, which processes data in a computer system having at least one processor, and a method for processing data utilizing a cache, are disclosed. The cache comprises a first array such as a tag array, a second array such as a data array, and a pointer for pointing to a portion of the second array that is associated with a portion of the first array, wherein the portion of the second array comprises the data to be processed, and wherein the number of times the at least one processor must undergo a first transfer latency is reduced. This is done by incorporating a prefetch mechanism within the cache. The computer system may include a plurality of processors with each data entry in the data array having an owner bit for each processor. The memory controller may also include a line preloader for prefetching data into the cache. Also, this design can be used in both single processor and multiprocessor systems.

Abstract: A hardware function performed in the data link control layer first determines if a received frame is an IP frame requiring IPSec processing, and if it is, places the IPSec frame on a separate receive queue for subsequent inbound processing. The hardware function further determines if a frame to be transmitted is an IP frame requiring IPSec outbound processing, and if it is, places the IPSec frame on a separate transmit queue for subsequent outbound processing. To determine if an IP frame is an IPSec frame, the hardware function examines both the type field in the Medium Access Control (MAC) header and the protocol field in the IP header, both at the data link control layer. Once IPSec and non-IPSec traffic are separated at the data link layer into different receive or transmit queues, a hardware assist component processes the IPSec data frames in parallel with the processing of non-IPSec data frames by the processor in the network device.

Abstract: A data processing system and method are disclosed for prohibiting an unauthorized user from modifying a priority level associated with a client computer system. The priority level is utilized by a client computer system during transmission of the client's data over a network. One of a plurality of priority levels is associated with the client computer system. The plurality of priority levels includes a higher priority level and a lower priority level. The client computer system associates the priority level with the data transmitted by the client computer system over the network. The data associated with the higher priority level is typically transmitted prior to data associated with the lower priority level. In response to an attempt to modify the associated priority level, the client determines whether the attempt is being made by an approved user. In response to a determination that the attempt is not being made by an approved user, the attempted modification of the priority level is prohibited.

Abstract: An apparatus for providing I/O support to a computer system and a method of use thereof is disclosed. The apparatus in accordance with the present invention includes an internal control element located within the apparatus. The control element allows the apparatus in accordance with the present invention to relinquish ownership of the associated I/O devices for the purpose of being used by another computer. Accordingly, through the use of the apparatus in accordance with the present invention, expensive KVM switches and cabling, along with the accompanying I/O devices, are no longer needed to provide I/O support for computer networks. A first aspect of the present invention provides an apparatus for providing I/O support to a computer system. The apparatus comprises an I/O device and an internal control element coupled to the I/O device for relinquishing ownership of the I/O device from the apparatus to the computer network.

Abstract: A heat sink retention assembly including a spring, a spring retainer, and a spring displacement limiter. The spring retainer maintains the spring in a compressed state in which a contact portion of the spring applies a force to the heat sink. The compressed state is characterized by a predetermined spring displacement and exerted force. The spring displacement limiting mechanism prevents displacement of the compressed spring substantially beyond the predetermined spring displacement. The displacement limiting mechanism may comprise a separate component such as a spacer structure or may be integrated into the configuration of the spring itself. In one spacer structure embodiment, the spacer has a vertical dimension that is determined by the difference between the total spring displacement possible and the predetermined spring displacement required to deliver the predetermined force to the heat sink.

Abstract: In a data processing system, an object is displayed on a display coupled to the data processing system. Also displayed, is a multiple-point cursor having at least first and second pointing spots. The multiple-point cursor is typically positioned by user manipulation of a pointing device, such as a mouse. In response to a user indication, such as a mouse click, a first operation is performed on the displayed object if the first pointing spot is positioned over the object during the mouse click. Similarly, a second operation is performed on the displayed object in response to a user indication while the second pointing spot of the multiple-point cursor is positioned over the object on the display. Such first and second operations may include a copy operation and a move operation.

Abstract: An installation/removal structure for use with a generally rectangular peripheral device which may be temporarily installed within a portable data processing system. An engagement structure is provided within an interior portion of the portable data processing system and an electrical connector is mounted proximate to the engagement structure within the portable data processing system. An elongate flexible wire bail is swingably mounted across one end of the peripheral device, such that the elongate flexible wire bail can be engaged with the engagement structure by swinging the bail to a first position such that the peripheral device is held in electrical engagement with the electrical connector and when swung to a second position disengages from the engagement structure and may be utilized to remove the peripheral device from the portable data processing system.

Abstract: Data destruction resulting from the conversion of a floppy disk can be prevented during a low-power consumption mode in which the FDD is powered off. The present invention is also designed to prevent data destruction resulting from the conversion of a floppy disk during a low-power consumption mode in which an FDC and an FDD are stopped. In the process of returning to a normal operation mode, an I/O address showing a change line status register of the FDC is set to a stored register of the trap logic (status 173). When the process returns to the normal operation mode and an access to the first status register is trapped, a change line status flag value is rewritten (status 174). The faked OS/driver invalidates the floppy disk allocation information in the main memory.

Abstract: A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.