Patents Represented by Attorney Martin Penilla & Gencarella, LLP

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  • Automatic generators for verilog programming
    Patent number: 7770147
    Abstract: A method for generating hardware description language source files is provided. The method includes extracting an input/output (I/O) list and building a port list declaration file from the I/O list. The method also includes building a default instantiation file according to renaming rules and interpreting coding constructs to determine both variable types and sizes. The method further includes generating a sensitivity list.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: August 3, 2010
    Assignee: Adaptec, Inc.
    Inventors: Marc Spitzer, John Packer