Abstract: An invention is provided for a carrier head that includes a metal plate having an opening formed in a central location. The metal plate has a wafer side, which faces the backside of a wafer during a CMP operation, and a non-wafer side. Positioned above the non-wafer side of the metal plate, and located above the opening in the metal plate, is a bladder or membrane. To facilitate uniformity during polishing, an inflating pressure is applied to the bladder, or membrane, that is substantially equivalent to a polishing pressure utilized during the CMP operation. To facilitate transporting the wafer, a vacuum can be applied to the opening in the metal plate to adhere the wafer to the carrier head. Further, to release the wafer from the carrier head, the bladder, or membrane, can be inflated such that it protrudes through the opening in the metal plate.

Abstract: Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit.