Abstract: Disclosed is a coaxial connector consisting of a back nut, outer and inner terminals, and an insulator. The back nut is made of a single tubular piece and does not enclose any further parts. In connecting a coaxial cable to the connector, the cable is inserted through the back nut, and a portion of the outer conductor at the end of the cable is flared and shaped along a tapered clamping face of the back nut. The back nut is then axially displaced, as by threading the back nut over the outer terminal, to clamp the flared end of the outer conductor of the coaxial cable between the outer terminal of the connector and the back nut thereof.
Abstract: A multi-port, electrical connector (100) includes a housing (105) having cable ports (122–128) for coaxial cables (421–428) on a cable side (101) of the housing and male push-on ports (271–278) for female connectors (801) on a male side (202). Each cable port has nonstandard internal threads (160). Each coaxial cable is terminated with a cable adapter (120). A coaxial cable-cable adapter combination is removably secured to each cable port by a clamp nut (130) having nonstandard external threads (660). Each coaxial cable-cable adapter combination is individually field replaceable. Another multi-port electrical connector (1000) includes a housing (1005) having male, push-on ports (1021–1028) on a male side (1001) of the housing and printed wiring board (PWB) ports (1171–1178) on a PWB side (1102). Each PWB port includes a straight PWB pin (1181–1188) for insertion into a hole in a PWB (1301).
Abstract: A tamper-resistant coaxial terminator includes an inner body rotatably captivated within an outer shield. A deformable portion of the inner body extends within an annular recess formed in the outer shield. An optional RF port, containing a resistor, is press-fit within the inner body. The RF port, or alternatively, the inner body, is internally-threaded for engaging the outer conductor of an equipment port. A seal ring extends over the outer conductor of the equipment port and is urged by the outer shield to directly engage the internally-threaded portion of the terminator. A seal is also optionally disposed between the outer shield and the inner body to minimize moisture induced corrosion. A shipping cap, usable at either end of the terminator, helps protect the terminator during shipment and prevents entry of debris.
February 18, 2005
Date of Patent:
December 5, 2006
Corning Gilbert Inc.
Donald Andrew Burris, Brian L. Kisling, William B. Lutz
Abstract: A coaxial connector includes a removable back nut, an outer body, and a center conductor supported within the outer body by a dielectric. The center conductor includes a female socket for receiving an exposed inner conductor of a coaxial cable, and a compression member compresses the female socket to seize the inner conductor as the back nut is secured to the outer body. In use, a prepared end of a coaxial cable is inserted through the back nut, and the end portion of the outer conductor of the coaxial cable is flared outwardly. As the back nut is tightened onto the outer body, the flared end of the outer conductor is directly clamped between integral clamping surfaces of the back nut and outer body. As the back nut is tightened, the compression member simultaneously engages the female socket to seize the inner conductor.
Abstract: A surge-protected coaxial termination includes a metallic outer body, a center conductor extending through a central bore of the outer body, and a spark gap created therebetween to discharge high-voltage power surges. A pair of dielectric support insulators support the center conductor on opposite sides of the spark gap. High impedance inductive zones surround the spark gap to form a T-network low pass filter that nullifies the additional capacitance of the spark gap. An axial, carbon composition resistor is disposed inside the outer body, and inside the dielectric insulator to absorb the RF signal, and prevent its reflection. The resistor extends co-axially with the center conductor, and one end of the resistor is electrically coupled thereto. A blocking chip capacitor extends radially from the opposite end of the resistor to the grounded outer body.
Abstract: Cable connector for coaxial cable, comprising a bushing (2) for providing an axial displacement of parts (4,5,6,7,8) in the connector, whereby these parts are brought into mechanical and/or electrical engagement with the coaxial cable. The axial displacement is provided by screwing a thread (10) provided on the bushing (2) onto a corresponding thread (9) provided on the main body (1) of the connector. By providing said threads (9,10) as multiple-start threads, the assembly time can be substantially reduced.
Abstract: A circuit and a method for adding an 8-bit operand to a 16-bit operand are disclosed such that the number of machine cycles required by a data processor to perform such an addition is reduced. The 8-bit operand and the least significant byte of the 16-bit operand are added together within an 8-bit adder circuit to generate the least significant byte of the result. Simultaneously, the most significant byte of the 16-bit operand is stored in a temporary register and is also input to an increment/decrement network. The adder circuit, after a given delay time, generates a carry signal depending on whether a carry-out was produced by the addition. The carry signal and the sign bit of the 8-bit operand control the mode of operation of the increment/decrement network and determine whether the increment/decrement network or the temporary register will be selected to provide the most significant byte of the result.
September 5, 1978
Date of Patent:
May 13, 1980
R. Gary Daniels, Fuad H. Musa, W. Bryant Wilder, Jr., Michael F. Wiles, Thomas H. Bennett
Abstract: A circuit for extracting a low frequency signal component from a composite signal is disclosed which uses a digital averaging technique for filtering out higher frequency components. An analog to digital converter receives a composite analog signal and provides a digital output signal. The composite analog signal is sampled during periodic intervals or sample periods. The digital output signal of the analog to digital converter is coupled to one input port of an adder/subtractor circuit and to the input of a sample register. The sample register stores the digital output signal and outputs the stored signal, delayed by a predetermined number of sample periods, to a second input port of the adder/subtractor. A storage register is used to store a running average which is equal to the sum of the digital signals received during the most recent predetermined number of sample periods. The average signal stored by the storage register is fed back to a third input port of the adder/subtractor.
Abstract: A method and an apparatus are disclosed which employ digital techniques to approximate a multiplication of an analog signal by a sine wave of an appropriate frequency for detecting the analog signal. The analog signal is converted to a digital representation which includes a binary sign bit and a plurality of binary magnitude bits. The sign bit of the digital representation is selectively complemented by an inverting logic gate which operates under the control of a square wave having the appropriate frequency of the sine wave which is being approximated. The selective complementation of the sign bit of the digital representation functions to multiply the digital representation by +1 or -1 as determined by the status of the square wave signal. The resulting digital representation is latched at periodic intervals for further processing of the detected signal which results from the quasi digital multiplication.
Abstract: A digital-to-analog converter circuit suitable for implementation as an integrated circuit in integrated-injection-logic form, and a method for regulating the collector current in a plurality of integrated-injection-logic transistors are disclosed. A plurality of switching transistors are connected to digital input terminals and the currents conducted by the plurality of switching transistors are summed to yield an analog output current. An injection bar shared by each of the switching transistors provides drive current to the plurality of switching transistors. The injection bar is also shared by one or more reference transistors, the current in which is determined by a current source. A feedback circuit is used to regulate the bias of the common injection bar such that the current conducted by each switching device corresponds to the current conducted by each reference device.
Abstract: An adder provides either binary or binary coded decimal operation under the selection of a control input. The data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits. Outputs, in addition to the four bit result, include carry propagate and carry generate signals for the four bit group. Binary operation is conventional. For binary coded decimal operation, the adder corrects an initial binary result to the binary coded decimal format by adding six when there is a group carry generate signal present thus forming an intermediate result. This intermediate result is formed before the occurrence of the carry in from a preceding stage. In the final stage of the adder, the intermediate result is incremented to form the final four bit result if there is a carry in.
Abstract: A dual function capability is incorporated into one input of an emitter coupled logic gate to allow a user to selectively enable the logic circuit to operate in a multifunction mode. The dual function input can recognize both normal binary voltage levels and operate as a conventional input for digital information, and also recognize voltage levels not within the normal binary voltage levels and modify the circuit function correspondingly.
July 8, 1977
Date of Patent:
September 11, 1979
Jack L. Anderson, Frank J. Swiatowiecz, Marvin A. Glazer
Abstract: Combining a differential PNP transistor pair for receiving external digital signals with an NPN output transistor in an I.sup.2 L configuration connected to the output of the differential pair provides a simple, high-speed, and versatile digital logic to I.sup.2 L interface circuit. The interface circuit is applicable to almost any digital logic series and also to analog inputs as they provide inputs into I.sup.2 L circuitry.
Abstract: A circuit is disclosed which provides first and second control voltages for controlling the gains of first and second variable gain amplifiers such that the relative gains provided by the first and second amplifiers can be varied while maintaining the total power gain provided by the first and second amplifiers substantially constant. The first and second control voltages are generated by passing first and second primary currents across semiconductor junctions. The first and second primary currents are controlled respectively by first and second secondary currents, the secondary currents being substantially proportional to the square of the respective primary current. The circuit allows the ratio of the secondary currents to be varied while maintaining the sum of the secondary currents substantially constant. The primary currents are thereby varied such that the sum of the squares of the primary currents remains substantially constant.
Abstract: An integrated circuit in which the Hall-Effect device and the sensing circuit can be incorporated on a single monolithic chip includes a Hall-Effect generator responsive to a magnetic flux change for generating a Hall-Effect voltage. A differential amplifier and current mirror circuit are coupled to the Hall-Effect device in order to vary or track the threshold voltage of the differential amplifier circuit in accordance with the output voltage from the Hall-Effect device irrespective of current changes in the Hall-Effect device due to temperature variations.
Abstract: An expandable array multiplier is disclosed using an asynchronous, sequential add technique for multiplying two numbers in either straight magnitude or two's complement notation. First and second control terminals are provided for simplifying expansion to larger array sizes. The control terminals can be programmed to select either two's complement or straight magnitude multiplication. For a two's complement multiply, the control terminals are programmed according to the relative position of the particular multiplier within an expanded array such that the proper two's complement correction terms are generated within a particular multipler. A carry-lookahead technique is used to further improve multiplier performance.
Abstract: Disclosed is a latching type sense amplifier to be used with a static IFGET random access memory which provides an improved memory circuit. The sense amplifier employs a pair of depletion mode devices which serve both as load devices for the latch and as means for coupling a pair of bit lines to the sense amplifier. Prior to sensing, both the bit lines and the switching nodes of the latch are precharged and balanced. The selection of a memory cell induces a small differential voltage across the bit lines, causing one of the depletion mode load devices to be more conductive than the other. When the latch is enabled, regenerative amplification causes the latch to seek one of two stable states as determined by the relative conductivities of the two depletion mode load devices, thereby latching the state of the data stored in the selected memory cell.
Abstract: A driver circuit that permits full duplex transmission of digital data on a single signal line includes means for enabling a receiver of a station having a transmitter and a receiver to ignore outgoing digital signals from the transmitter of the same station and receive incoming signals. The circuit includes means that combine the incoming and outgoing digital signals in the signal line to form a composite multi-level signal which shifts between predetermined amplitude levels and means that recover the incoming digital signals from the composite signal. An offset bias level is added within the receiver signal processing to the transmitter pulse level to reduce noise susceptibility. Using such a circuit a full duplex transmission system of a plurality of stations connected to a common single signal line is provided. Such a system can be operated in a broadcast mode wherein one station can transmit signals to the remainder of stations.