Abstract: An apparatus is provided to reduce the amount of EMI generated by a circuit. The grounding of an enclosure is improved by providing a number of shaped protuberances, the protuberances having an end that penetrates a conductive region of a circuit board, such that when the circuit board is mounted to the support member, the protuberances make a penetrating electrical contact and provides for additional ground paths, thereby reducing the EMI generated by the assembly.

Abstract: Automatic shelf-to-shelf address assignment is provided for a plurality of disk drive supporting shelves that are removably contained within a multi--shelf cabinet. Error detection apparatus detects failure in the automatic assignment of shelf addresses. An address input of shelf-N receives a shelf addressing voltage from shelf N+1. Shelf-N checks to ensure that the received shelf-N address voltage is within a correct range. Where-N now increases its shelf-N address by one and applies this incremented address to an address input of shelf-N+1. Accuracy of the shelf-N+1 address input is checked, as are the cable/connectors that connect shelf-N to shelf-N+1. ADC and ADC techniques are used, and operation of the automatic address assignment system is timed.

Abstract: An architecture, module set and platform to provide total power protection from utility disturbances. Power supplies employing the invention are built on power buses for utility AC input, battery DC input and conditioned AC output housed in the platform and employ modular line-to-AC-or-DC power-factor-correcting converters and battery/charger sets either housed in the platform or integrated as part of the front end power supply for a critical load such as a computer.

Abstract: A cable used for transmitting the signals of a communications bus, such as a SCSI bus, having arbitration control signals subject to a wired-or glitch--such as the SCSI BSY signal. Low characteristic impedence conductors ensure that voltage reflections resulting from the deassertion of the BSY signal do not exceed a minimum threshold signal assertion voltage, allowing an increase in the maximum length of the SCSI bus cable.

Abstract: This disclosure describes an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined the system actually stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This disclosure also describes the test coupon, which is designed to uniformly dissipate the heat created during stress cycling.

Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.

Abstract: A command queueing apparatus for directing address and command information amongst the various interfaces, or consumers, on a multi-CPU node in a computer system. The apparatus includes a core queue containing core queue entries, each core queue entry corresponding to a pending system bus operation. Each core queue entry includes one or more consumer information fields specific to each consumer. Also included is a plurality of virtual queues, each virtual queue corresponding to a consumer, each virtual queue having a virtual queue entry. A virtual queue entry for a consumer is a subset of the fields of a core queue entry, the subset of fields including the consumer information fields for the consumer corresponding to the virtual queue.

Abstract: Computer systems using a processor that is capable of operating in a system management mode (SMM) employ a dedicated system management RAM (SMRAM). The processor uses the SMRAM when the processor is performing a task associated with the SMM. The processor is capable of generating a range of system addresses. The range includes a particular subrange of system addresses that are used for accessing the SMRAM. A memory controller decodes the system addresses generated by the processor and enables access to the SMRAM, regardless of whether the processor is operating in the SMM, when the controller decodes a system address of the particular subrange. The range of system addresses also includes a second subrange. The memory controller also enables access to the SMRAM when the processor is operating in the SMM and the controller decodes a system address of the second subrange. The memory controller indicates to the processor whether data associated with the enabled SMRAM can be stored in a cache memory.

Abstract: A memory controller circuit for use in a computer system provides memory address and control signals to a single in-line memory module (SIMM) connector. The SIMM connector can hold a SIMM that has dynamic random access memories (DRAMs) mounted on one or both sides. The SIMM connector provides a channel of signals to both sides of the SIMM. A driver associated with each channel receives a memory address and control signal. Each driver either drives a buffered memory signal to the associated channel or is placed in a high impedance state, depending upon whether a SIMM is in the SIMM connector. If a SIMM is in the connector, the driver associated with one of the channels is placed in the high impedance state if it is determined that the SIMM is single-sided. A programmable disabling means provides a driver enable signal to each driver. When the driver enable signal is asserted, the corresponding driver is in an enabled state. A deasserted driver enable signal places the corresponding driver in a disabled state.

Abstract: Electrical test method and apparatus for performing the method. The method operates to determine an electrical characteristic of a node (2) disposed upon a surface of a substrate (3), such as a printed wiring board (PWB). The method includes a first step of providing relative motion between a probe (1) and the surface of the PWB. A second step measures the electrical characteristic during a time that there is relative motion between the probe and the surface of the PWB. In one embodiment of the invention the step of measuring measures capacitance while in another embodiment of the invention the step of measuring measures charge capacity. The step of providing relative motion, in one embodiment of the invention, includes the steps of maintaining the PWB stationary while linearly translating the probe over the surface. In another embodiment of the invention the step of providing relative motion includes the steps of maintaining the probe stationary while moving the PWB.

Abstract: A very thin portable computer includes a computer housing for holding electronic components and a battery housing movably mounted external to the computer housing, the battery housing adapted for holding batteries for supplying power to the electronic components. The battery housing is rotatably mounted on the computer housing such that the battery housing rotates between a closed position wherein the battery housing covers the rear side of the computer and an open position wherein the battery housing exposes connectors on the computer housing and elevates the rear side of the computer housing to an angle convenient for typing.

Abstract: An apparatus and method for caching SMRAM in an Intel.RTM. CPU employing system management mode. A cache for the CPU includes a plurality of data entries and an SMRAM status bit corresponding to each data entry. The SMRAM status bit is set if the data entry holds data in SMRAM, and reset if the data entry does not hold data in SMRAM. The SMRAM status bit distinguishes SMRAM data from system memory data in the cache, thereby eliminating cache coherency problems.

Abstract: A cable used for transmitting the signals of a communications bus, such as a SCSI bus, having arbitration control signals subject to a wired-or glitch--such as the SCSI BSY signal. High propagation speed conductors increase the propagation speed of the BSY signal, resulting in a proportionate increase in the maximum length of the SCSI bus cable while maintaining adherence with the SCSI bus timing specifications.

Abstract: A storage system having a plurality of disks arranged in a RAID array with one of said disks being a replacement disk. A method and apparatus for restoring the contents of the replacement disk without interrupting concurrent access to the RAID array. An access request by a user application to a data block in the replacement disk results in regeneration and reconstruction of the accessed data block. In addition, the systematic reconstruction of data or parity blocks not yet accessed by the user application occurs by locating status bits associated with each data and parity block of the new disk.

Abstract: A DRAM memory controller for a printer having a single host CPU and a bitmap memory. The CPU initiates data transfers synchronously to a system clock for filling the bitmap memory, and a DMA controller initiates data transfers asynchronously to the system clock for transferring data from the bitmap memory to a print engine. The controller includes a first sequencer for controlling synchronous data transfers initiated by the host CPU, a second sequencer for controlling asynchronous data transfers initiated by the DMA controller, a refresh request generator for generating a refresh request signal which is asynchronous to the system clock, and a third sequencer for controlling memory refresh and for controlling arbtitration betwween the first, second, and third sequencers. Also provided is a method of transferring data between a bitmap memory and a print fifo in a printer.

Abstract: A method and apparatus is provided for use in an asynchronous bus interface capable of multiple or single width transfers and controlled by handshake signals, in which the bus transaction may include multiple successive data transfers delineated by a data strobe, and in which each data transfer is terminated by a data handshake signal, and in which data transfers for different cycle types incur different propagation delays, including bus buffering apparatus for directing transfers over single and multiple width busses, and an asynchronous bus controller for returning data handshake signals with individualized timing characteristics in response to the master data strobe and the cycle type of the transaction, such that each successive data transfer is completed in the minimum time that propagation delays, as indicated by the cycle type, will allow, in order to maximize bus throughput.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: Dynamic focus circuits for generating a dynamic focus signal for focusing an electron beam on a CRT, the signal being proportional to a function of the vertical deflection Y and horizontal deflection X of the beam according to X.sup.2 +Y.sup.2 +X.sup.2 f(Y) or X.sup.2 +Y.sup.2 +Y.sup.2 f(X), where f(Y) or f(X) is a positive symmetric function. The resultant dynamic focus signal has increased magnitude as the beam moves away from the center of the screen, thus providing proper focusing at the corners of the screen as well as at the center and sides of the screen.

Abstract: This disclosure describes an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined the system actually stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This disclosure also describes the test coupon, which is designed to uniformly dissipate the heat created during stress cycling.

Abstract: A PC board cartridge for a computer terminal, the cartridge including a casing for holding a PC board with a connector mounted thereon. A handle is pivotally mounted on the casing along an axis extending in a plane that extends perpendicular to a major surface of the board and intersects the board at the connector. The PC board cartridge preserves electrical and mechanical connector integrity by providing a handle for removal which applies generally equal forces across the connector during removal. In addition, no additional hardware is required for assembly, installation, or removal of the cartridge.