Patents Represented by Attorney Matt Talpis
  • Patent number: 8310953
    Abstract: A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a “Fiber Channel over Ethernet” communication capability and methodology. Device driver software manages a Fiber Channel to Ethernet and Ethernet to Fiber Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Aaron C. Brown, Scott M. Carlson, Kevin J. Gildea, Roger G. Hathorn, Jeffrey W. Palm, Renato J. Recio
  • Patent number: 8307048
    Abstract: A network system supports multiple network communication protocols. An Ethernet component gateway in a Fiber Channel over Ethernet (FCoE) initiator system converts FCoE data packets from host devices to Fiber Channel over Internet Protocol (FCIP) data packets for transmission to a Storage Area Network (SAN) target system. The SAN target system may include a target Fiber Channel (FC) storage device and a SAN component gateway. The SAN component gateway converts FCIP data packets to SAN data packets for use by the target FC storage device. The SAN data packets may be either FC protocol data packets or FCoE protocol data packets. The SAN target system may provide for discovery of target FC storage device adapter information.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Aaron C Brown, Scott M Carlson, Daniel G Eisenhauer, Roger G Hathorn, Jeffrey W Palm, Renato J Recio, Gregory J Tevis
  • Patent number: 8300704
    Abstract: An information handling system (IHS) may include a processor with multiple compute elements that decode pictures from an encoded video bitstream. Each compute element may perform a different part or sequential stage of a picture decoding process to obtain decoded pictures. A memory includes a decoded picture buffer that associates with a first stage of the sequential stages. The memory may also include respective decoded picture buffer snapshots for sequential stages other than the first sequential stage. A last sequential stage provides fully decoded pictures to a decoded picture pool in memory. The decoded picture buffer and decoded picture buffer snapshots may store pointers to decoded pictures in the decoded picture pool that the sequential stages need to perform decoding of pictures. In this manner, the sequential stages may share decoded pictures that the decoded picture pool stores.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yu Yuan, Rong Yan, Sheng Xu, Xing Liu, Huo Ding Li
  • Patent number: 8266386
    Abstract: A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor integrated circuit including multiple processors with respective processor cache memories. The design structure may specify enhanced cache coherency protocols to achieve cache memory integrity in a multi-processor environment. The design structure may describe a processor bus controller manages cache coherency bus interfaces to master devices and slave devices. The design structure may also describe a master I/O device controller and a slave I/O device controller that couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventor: Bernard Charles Drerup
  • Patent number: 8255669
    Abstract: An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Robert Alan Philhower, Raymond Cheung Yeung
  • Patent number: 8245018
    Abstract: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventor: Dung Quoc Nguyen
  • Patent number: 8244515
    Abstract: A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew Earl Fernsler, Hans Mikael Jacobson, Johny Srouji, Todd Swanson
  • Patent number: 8244568
    Abstract: A scheduling system includes a client calendar application that a meeting organizer employs to send a request for free time form to prospective participants of a future meeting via email. The client calendar application receives completed request for participant free time forms back from the prospective participants via email. The client calendar application parses the completed free time forms and determines a consensus free time when all prospective participants are free for the meeting.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph G. Baron, Frank Battaglia, Jerrold Martin Heyman, Michael Leonard Nelson, Andrew Geoffrey Tonkin
  • Patent number: 8214660
    Abstract: A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Warren D. Dyckman, Michael Jay Shapiro
  • Patent number: 8201159
    Abstract: An information handling system (IHS) employs a compiler methodology that seeks to improve the efficiency of code that executes in a multi-core processor. The compiler receives source code and converts the source code for execution using data parallel select operations that perform well in a single instruction multiple data (SIMD) environment. The compiler of the IHS may apply one or several optimization processes to the code to increase execution efficiency in a parallel processing environment.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventor: Michael Karl Gschwind
  • Patent number: 8196127
    Abstract: An information handling system (IHS) employs a compiler methodology that seeks to improve the efficiency of code that executes in a multi-core processor. The compiler receives source code and converts the source code for execution using data parallel select operations that perform well in a single instruction multiple data (SIMD) environment. The compiler of the IHS may apply one or several optimization processes to the code to increase execution efficiency in a parallel processing environment.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventor: Michael Karl Gschwind
  • Patent number: 8185371
    Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Adil Bhanji, Sean Michael Carey, Jack Dilullo, Prashant D Joshi, Don Richard Rozales, Vern Anthony Victoria, Albert Thomas Williams
  • Patent number: 8108618
    Abstract: An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus controller manages cache coherency bus interfaces to master devices and slave devices. In one embodiment, a master I/O device controller and a slave I/O device controller couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller. In one embodiment, the processor bus controller blocks partial responses that it receives from all devices except the slave I/O device from being included in a combined response that the processor bus controller sends over the cache coherency buses.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventor: Bernard Charles Drerup
  • Patent number: 8103852
    Abstract: An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of internal operations data. The BUIQ includes a unified issue queue UIQ 0 and a unified issue queue UIQ 1. The BUIQ may manage a particular VSU store instruction from one UIQ to determine data dependencies and employ the other UIQ to determine address dependencies of that particular VSU store instruction. The UIQs employ a dependency matrix including a dependency array. The dependency array data maintains both data and address dependency information. The particular VSU store instruction issues to execution units such as VSUs for data dependency information and load store units (LSUs) for address dependency information. A particular VSU store instruction may execute to provide data dependency information independent of address dependency information.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: James Wilson Bishop, Mary Douglass Brown, William Elton Burky, Todd Alan Venton
  • Patent number: 8073668
    Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: December 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey William Kellington, Prabhakar Nandavar Kudva, Naoko Pia Sanda, John Andrew Schumann
  • Patent number: 8073669
    Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: December 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew Earl Fernsler, Hans Mikael Jacobson, Johny Srouji, Todd Swanson
  • Patent number: 8055761
    Abstract: A client information handling system (IHS) connects to a network in a manner that provides transparent network connectivity. In one embodiment, the client IHS includes a polling application that monitors the network connection to determine if the client IHS exhibits a connected status or a disconnected status. An interceptor application in the client IHS permits transmission of a request for a network task from the client IHS if the client IHS currently exhibits a connected status. However, the interceptor application intercepts and stores a request for a network task if the client IHS currently exhibits a disconnected status. At a later time when the client IHS again exhibits a connected status, the interceptor application transmits the stored request over the network. In this manner, the user of the client IHS experiences transparent network connectivity and need not worry with respect to the network connection status of the client IHS at any particular point in time.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Janel Guillory Barfield, Nancy N. Li
  • Patent number: 8010656
    Abstract: A calendar system includes a calendar requester client and a calendar owner client that couple to a calendar server via one or more networks therebetween. In one embodiment, when the calendar server denies a particular calendar requester access to the calendar owner's calendar, the calendar server transmits a denial notice to the calendar owner and allows the calendar owner to dynamically add the particular calendar requester to a list of approved requesters on the calendar server.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joseph G. Baron, Frank Battaglia, Jerrold Martin Heyman, Michael Leonard Nelson, Andrew Geoffrey Tonkin
  • Patent number: 8010334
    Abstract: A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) generation, cycles per instruction (CPI) error, clustering and other programs. The test system also includes CPI stack program software that generates CPI stack data that includes microarchitecture dependent information for each instruction interval of workload program software. The CPI stack data may also include an overall analysis of CPI data for the entire workload program. IC designers may utilize the benchmark software and CPI stack program to develop a reduced representative workload program that includes CPI data as well as microarchitecture dependent information.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert H Bell, Thomas W Chen, Jr., Venkat R Indukuru, Alex E Mericas, Pattabi M Seshadri, Madhavi G Valluri
  • Patent number: 8006070
    Abstract: An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Robert Alan Philhower, Raymond Cheung Yeung