Abstract: A target computing system 10 is adapted to support a register window architecture, particularly for use when converting non-native subject code 17 instead into target code 21 executed by a target processor 13. A subject register stack data structure (an “SR stack”) 400 in memory has a plurality of frames 410 each containing a set of entries 401 corresponding to a subset of subject registers 502 of one register window 510 in a subject processor 3. The SR stack 400 is accessed by the target code 21 executing on the target processor 13. The SR stack 400 stores a large plurality of such frames 410 and thereby avoids overhead such as modelling automatic spill and fill operations from the windowed register file of the subject architecture. In one embodiment, a target computing system 10 having sixteen general purpose working registers is adapted to support a register window architecture reliant upon a register file containing tens or hundreds of subject registers 502.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary multiprocessor computing system provides memory and multiple processors, and a set of controller/translator units TX1, TX2, TX3 arranged to convert respective application programs into program threads T1, T2, etc., which are executed by the processors. Each controller/translator unit sets a first mode where a single thread T1 executes on a single processor P1, orders a second mode for two or more threads T1, T2 that are forced to execute one at a time on a single processor P2 such as by setting affinity with that processor, and orders a third mode to selectively apply active memory consistency protection in relation to accesses to explicit or implicit shared memory while allowing the multiple threads T1, T2, T3, T4 to execute on the multiple processors.

Abstract: A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

Abstract: An apparatus, system and method of executing a monolithic application program successfully on a grid computing system are provided. Before the program is executed on the grid computing system, the program is executed on a computer on which the program has previously been successfully executed. During its execution, the program is monitored to collect its runtime information. The runtime information is provided to the grid computing system. With this information the grid computing system is able to successfully execute the program.

Abstract: A dynamic binary translator 19 converts a subject program 17 into target code 21 on a target processor 13. For a multi-threaded subject environment, the translator 19 provides a global token 501 common to each thread 171, 172, and one or more sets of local data 502, which together are employed to coordinate access to a memory 18 as a shared resource. Adjusting the global token 501 allows the local datastructures 502a,b in each thread to detect potential interference with the shared resource 18.

Abstract: The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.

Abstract: During program code conversion, such as in a dynamic binary translator, automatic code generation provides target code 21 executable by a target processor 13. Multiple instruction ports 610 disperse a group of instructions to functional units 620 of the processor 13. Disclosed is a mechanism of preparing an instruction group 606 using a plurality of pools 700 having a hierarchical structure 711-715. Each pool represents a different overlapping subset of the issue ports 610. Placing an instruction 600 into a particular pool 700 also reduces vacancies in any one or more subsidiary pools in the hierarchy. In a preferred embodiment, a counter value 702 is associated with each pool 700 to track vacancies. A valid instruction group 606 is formed by picking the placed instructions 600 from the pools 700. The instruction groups are generated accurately and automatically. Decoding errors and stalls are minimized or completely avoided.

Abstract: An improved architecture for a program code conversion apparatus and method for generating intermediate representations for program code conversion. The program code conversion apparatus determines which types of IR nodes to generate in an intermediate representation (IR) of subject code (10) to be translated. Depending upon the particular subject and target computing environments involved in the conversion, the program code conversion apparatus utilizes either base nodes, complex nodes, polymorphic nodes, and architecture specific nodes, or some combination thereof, in generating the intermediate representation.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

Abstract: A method for determining configuration information to be reported comprises accessing a table corresponding to a configuration resource associated with the configuration information, wherein the table comprises an entry for each hardware configuration definition to be built for the configuration resource, identifying a seed value in the table corresponding to the configuration resource, and modifying the seed value based on a result of processing each entry indicated by the table.

Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.

Abstract: Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.

Abstract: A performance-enhancing system and method of accessing file system objects are provided. The system and method entail determining a plurality of file system objects that are frequently being accessed. Each one of these file system objects has a pathname and an inode number. The inode number is used to locate the file system object on a storage system. The pathname of each file system object and its inode number are cross-referenced and cached. Having a whole pathname of a file cross-referenced with its inode number and entered into a memory allows the inode number to be obtained with one memory access instead of the many memory accesses that are usually required.

Abstract: Systems and methods for denying access to a data processing system by an intruder are provided. Input/output (I/O) on the intruder's connection may be taken over and responses mimicking a local terminal session passed back. On an attempted reconnect by the intruder, the user name and password used by the intruder to access the system may be captured. The password may then be changed on the edge system and the intruder's terminal session disconnected, or alternatively, continue to log the intruder's activity.

Abstract: An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

Abstract: A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.

Abstract: In program code conversion, particularly dynamic binary translation, subject code 17 is translated into target code 21 through a translator 19 for execution on a target processor 13. Selected portions of subject code, such as library functions SFuncA 172, are replaced by instead executing a portion of native code such as a native function NFuncA 282. The native function is native to the target processor 13. The method further includes executing a subject code portion such as a subject function SFuncB 173 in place of a native code portion such library function NFuncB 283. This reverse binding technique substitutes subject code for selected portions of the native code, particularly native library functions in order to keep control within the translator 19. This helps to maintain an accurate subject state in the translator 19, amongst other advantages.

Abstract: The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.