Abstract: According to one aspect of the invention, a method is provided for maintaining the state of a processor having a plurality of physical registers and a rename register map which stores rename pairs that associate architected and physical registers, the rename register map having a plurality of entries which are associated with the physical registers, individual entries having an architected register field, an architected status bit and a history status bit.

Abstract: The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.

Abstract: One aspect of the invention relates to an apparatus for detecting environmental faults in a computer system. In one version of the invention, the apparatus includes a means for measuring a physical parameter with a sensor coupled to the computer system, the sensor being associated with a sensor type and identification code; a means for transmitting a signal from the sensor to the computer system, the signal being responsive to the measurement; a means for determining whether an environmental fault condition exists by comparing the signal to a pre-determined threshold; means for determining an error type, identification code and sensor type; and a means for writing fault data to an environmental warning register, the fault data comprising the sensor type, identification code and error type.

Abstract: Module for the protection of software in a computer network comprising a microprocessor for implementing an access control to the software, said microprocessor being connectable via a parallel interface, particularly via a printer interface, with a network server, a programmable storage, being addressable by means of said microprocessor, in which a user limit code Xlimit is stored, and a device for processing said user limit code Xlimit and an actual user number under a processing software, said device being arranged in said module and being addressable by means of said microprocessor.

Abstract: The present invention relates to a high-density magnetic recording medium (or "media" as it is sometimes called) for a recording/reproduction system (such as thosed used in computer disk drives) and, more particularly, to a magnetic recording medium having a plurality of magnetic recording layers such that the uppermost layer is comparatively thinner and more densely structured than the lower magnetic recording layers. The present magnetic recording medium comprises a non-magnetic plated substrate, a non-magnetic underlying layer laminated on the plated substrate, a plurality of magnetic alloy layers including the uppermost layer laminated onto the underlying layer, a non-magnetic covering layer laminated onto the uppermost layer, and a lubricating layer formed onto the non-magnetic covering layer.

Abstract: A RISC-based microcontroller is described which uses "split" data buses in the functional areas of the ALU and the I/O peripheral control interface. Also, the "Harvard" architecture is applied with separate buses for instructions and operational data which are stored and supplied from separate memories, i.e., an instruction memory and a data memory. This architecture allows to run the microcontroller with timing and clocking schemes of higher frequencies resulting in faster speed and higher processing rates in MIPS. The different functional components of the microcontroller can be placed on a single VLSI chip while other designs with much less on-chip functions are also conceivable.

Abstract: An automatic analyzer in which a suitable transmission destination remote from a body of the automatic analyzer is selected in accordance with the contents of to be transmitted and the contents are transmitted to the transmission destination; a suitable operation control instruction is received from a suitable person on duty; and a suitable process is carried out to make it possible to improve analysis efficiency.

Abstract: According to the present invention, a comparison circuit for combining a plurality of data bits is provided. One version of the invention includes a comparator which provides a signal responsive to a comparison of the voltage states of at least two of the plurality of data bits, and an amplifier which is coupled to the comparator and compares the signal provided by the comparator to a reference voltage to provide an output signal, the reference voltage being between a high and a low voltage state.

Abstract: According to the present invention, there is provided a method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load.

Abstract: According to the present invention there is provided an encoder, which in one embodiment, includes a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value such that only one bit of the counter value changes each time the counter value is incremented, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In another embodiment of the invention there is provided a method for use with an encoder having a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In one embodiment, the method includes the steps of incrementing the counter value such that only one bit is changed each time the counter is incremented.

Abstract: According to the present invention, a method is provided for reading data from non-volatile memory in an electronic encoding device such that unauthorized access to the data is prevented. In one embodiment, the method includes the steps of writing a first set of data to the non-volatile memory; generating a voltage detect signal during the writing, the voltage detect signal being representative of a source voltage applied to the non-volatile memory; determining whether the writing was successful by evaluating the voltage detect signal; and reading data from the non-volatile memory responsive to the determination.

Abstract: A process is provided for use with a semiconductor testing apparatus having a vector generator which provides a sequence of vectors to a semiconductor device at a rate responsive to a timeset, a power supply which provides current to the semiconductor device and a current monitor which measures the current provided to the device. In one specific embodiment, the process includes setting the timeset to a first rate, conditioning the device by executing a plurality of vectors at the first rate, setting the timeset to a second rate, the second rate being slower than the first rate, and measuring the quiescent current while the timeset is set to the second rate.

Abstract: A computer-based method is provided for determining whether a semi-conductor device conforms to design requirements. In one embodiment, the method is based on data stored in a design database, and an automatic test equipment ("ATE") datalog. In a further embodiment, the method includes generating a requirements datalog responsive to the design database, generating a standard datalog responsive to the automatic test equipment datalog, and generating a conformance indication responsive to the requirements datalog and the standard datalog.