Patents Represented by Attorney, Agent or Law Firm Matthew M. Gaffney
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Patent number: 6834093Abstract: A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured to provide two reset signals. The two counter circuits are arranged to be clocked by a respective one of the two input signals, and further arranged to be reset by a respective one of the two reset signals. Further, the AND gate is arranged to perform an AND function on the overflow outputs of the first and second counter circuits to provide an status signal. If the status signal is high, the difference in frequency between the two input signals is less than the tolerance. If the status signal is low, the difference in frequency between the two input signals exceeds the tolerance.Type: GrantFiled: March 19, 2004Date of Patent: December 21, 2004Assignee: National Semiconductor CorporationInventor: Hon K. Chiu
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Patent number: 6831501Abstract: A current source circuit with common-mode differential gain boosting is provided. The current source circuit differentially provides first and second currents. The first current is produced by a first cascoded current source, and the second current is produced by a second cascoded current source. Each of the cascoded current sources comprises a current source transistor and a cascode transistor. The current source circuit has high output impedance utilizing gain-boosting techniques. A three-input differential amplifier forces a gate of the cascode transistor of each of the current source circuits to an approximately constant voltage. The three-input differential amplifier is configured to receive a bias signal. The current source circuit is arranged to servo both the gate and source of the cascode transistors in response to the bias signal.Type: GrantFiled: June 13, 2003Date of Patent: December 14, 2004Assignee: National Semiconductor CorporationInventor: Arlo Aude
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Patent number: 6823461Abstract: A method and system for transferring contexts from a previous access router (PR) to a new access router (NR) that is subsequently associated with a Mobile Node (MN). For example, transferred contexts may include, but are not limited to, Security, Quality of Service (QOS), Header Compression, and Buffers. A context is transferred from the PR to the NR. Any change in an element of the context is conveyed by the NR to the MN in a secure fashion, even though a Security Association does not yet exist between the NR and MN. The NR provides an authenticated security context update to the MN, e.g., advising when the type of encryption has changed from Triple Data Encryption Standard (DES) to DES. The NR utilizes the Security Association between the PR and the MN, to provide such an authenticated security context update to the MN over a RAN or a wireless LAN.Type: GrantFiled: June 27, 2002Date of Patent: November 23, 2004Assignee: Nokia CorporationInventors: Ram Gopal Lakshmi Narayanan, Govindarajan Krishnamurthi, Senthil Sengodan
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Patent number: 6791997Abstract: The present invention provides a medium access control (MAC) protocol for the collision-free transmission of packets into a channel, such that nodes are assigned time slots for collision-free transmission based on the knowledge that they acquire regarding the constituency of their local neighborhoods and the advertisements of the time slots when nodes in local neighborhoods will attempt to transmit again. The scheduling procedure may utilize an age of the network together with the unique identifiers of nodes. The candidate transmission times for each node are determined using a list of the subsequent transmission times advertised by other nodes. The node discards the advertised transmission times from the list of potential transmission times, and computes its candidate transmission times using a function that provides a varying (pseudorandom) distribution of outputs for a varying sample of inputs. This function ay be a hash function, an encryption function, or a table lookup function.Type: GrantFiled: August 26, 2002Date of Patent: September 14, 2004Assignee: Nokia CorporationInventors: David Beyer, Jose J. Garcia-Luna-Aceves
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Patent number: 6791484Abstract: A method and apparatus for system offset calibration using an overranging ADC is provided. The overranging ADC is configured to convert an analog signal into an intermediary digital signal. The conversion range of the overranging ADC is extended beyond the full dynamic range of the ADC system. The intermediary digital signal has more bits than the digital output signal. A digital fine offset adjustment circuit is configured to provide the digital output signal by digitally subtracting a fine offset from the intermediary digital signal and decoding the intermediary digital signal. The digital output signal has approximately no offset, and has approximately no loss in dynamic range.Type: GrantFiled: July 18, 2003Date of Patent: September 14, 2004Assignee: National Semiconductor CorporationInventors: Bumha Lee, Brian D. Segerstedt, Christina P. Phan
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Patent number: 6781450Abstract: The present invention is related to glitch reduction of the output of an auto-zero amplifier. The auto-zero amplifier may be used in a voltage regulator, and the glitch reduction in the auto-zero amplifier will result in reduced output ripple. The auto-zero amplifier stores an input offset during an auto-zero phase, so that the input offset can be corrected during an amplification phase. During the amplification phase, the gate-drain voltage of a first transistor is sampled onto a capacitor. During the auto-zero phase, the capacitor is used to maintain the same voltage across the gate-drain voltage of the first transistor that was present during the amplification phase. The capacitor maintains the gate-drain voltage during the auto-zero phase in order to compensate for the large step in voltage that would otherwise occur.Type: GrantFiled: March 7, 2003Date of Patent: August 24, 2004Assignee: National Semiconductor CorporationInventors: Mark J. Mercer, Paul Ranucci
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Patent number: 6777781Abstract: The operating temperature range for a vertical PNP transistor can be extended by applying cancellation techniques. The vertical PNP generates a first leakage current from the base-collector region. Another vertical PNP transistor is configured to generate a second leakage current, which is coupled to a current-mirror circuit. The output of the current-mirror circuit is configured to provide a cancellation effect on the first leakage current. The current-mirror circuit and vertical PNP may be configured such that the first leakage current is cancelled in a judicious amount, whereby the effects of leakage current and flare-out in the vertical PNP transistor are minimized or cancelled. The cancellation technique is applicable to temperature sensor circuits, thermal voltage generators, and bandgap circuits.Type: GrantFiled: April 14, 2003Date of Patent: August 17, 2004Assignee: National Semiconductor CorporationInventor: Perry Scott Lorenz