Abstract: A graphics processor capable of parallel scheduling and execution of multiple threads, and techniques for achieving parallel scheduling and execution, are described. The graphics processor may include multiple hardware units and a scheduler. The hardware units are operable in parallel, with each hardware unit supporting a respective set of operations. The hardware units may include an ALU core, an elementary function core, a logic core, a texture sampler, a load control unit, some other hardware unit, or a combination thereof. The scheduler dispatches instructions for multiple threads to the hardware units concurrently. The graphics processor may further include an instruction cache to store instructions for threads and register banks to store data. The instruction cache and register banks may be shared by the hardware units.

Abstract: A method of encoding receives an image and tiles the image into a set of tiles. Each tile includes a set of pixels. The method selects a first tile and determines a first set of values for the pixels in the first tile. The method separates the determined values of each pixel in the first tile into several streams. For a first stream, the method determines a bias value, and subtracts the bias value from each value within the stream, thereby generating a set of subtracted values. Typically, the subtracted values have one or more leading zeros, and the method preferably removes one or more of the leading zeros, thereby reducing the number of bits required to represent the subtracted values within the first stream. Thus, one or more of the values within the first stream is advantageously represented with fewer bits. Additional embodiments include an encoder for encoding data by using a reduced number of bits, and a system, and decoder, for transmission, reception, display, storage and/or retrieval.

Abstract: Configuration information is used to make a determination to bypass fragment shading by a shader unit of a graphics processing unit, the shader unit capable of performing both vertex shading and fragment shader. Based on the determination, the shader unit performs vertex shading and bypasses fragment shading. A processing element other than the shader unit, such as a pixel blender, can be used to perform some fragment shading. Power is managed to “turn off” power to unused components in a case that fragment shading is bypassed. For example, power can be turned off to a number of arithmetic logic units, the shader unit using the reduced number of arithmetic logic unit to perform vertex shading. At least one register bank of the shader unit can be used as a FIFO buffer storing pixel attribute data for use, with texture data, to fragment shading operations by another processing element.

Abstract: This disclosure describes techniques for removing vertex points during two-dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.

Abstract: Techniques for identifying and enhancing colors in a digital image associated with one or more target color shades. In an embodiment, the target color shades may include a shade of blue associated with the sky, a shade of green associated with outdoor foliage, or the color red. In an embodiment, the blue chroma (Cb) and red chroma (Cr) coordinates of a pixel are evaluated to determine whether to apply an enhancement factor. The enhancement factor may incorporate an exposure index (EI) auxiliary enhancement factor, a color temperature (D) auxiliary enhancement factor, and a luminance (Y) of each pixel. Further aspects for implementing the techniques in software and hardware are disclosed.

Abstract: The disclosure describes FGS video coding techniques that use cycle-aligned fragments (CAFs). The techniques may perform cycle-based coding of FGS video data block coefficients and syntax elements, and encapsulate cycles in fragments for transmission. The fragments may be cycle-aligned such that a start of a payload of each of the fragments substantially coincides with a start of one of the cycles. In this manner, cycles can be readily accessed via individual fragments. Some cycles may be controlled with a vector mode to scan to a predefined position within a block before moving to another block. In this manner, the number of cycles can be reduced, reducing the number of fragments and associated overhead. The CAFs may be entropy coded independently of one another so that each fragment may be readily accessed and decoded without waiting for decoding of other fragments. Independent entropy coding may permit parallel decoding and simultaneous processing of fragments.

Abstract: Interpolations systems and methods are disclosed. In a particular embodiment, a system is disclosed that includes an input to receive image data. The system also includes an image processing system responsive to the image data and including a demosaicing module. The demosaicing module is configured to use adaptive bi-cubic spline interpolation. The system further includes an output responsive to the image processing system and adapted to provide output data.

Abstract: This disclosure describes techniques for encoding data to compress image data to a reduced size. The techniques may be particularly effective in transcoding an image to a reduced size for transmission. An encoding device may transcode an image to an acceptable file size using bitrate control techniques that affect the entire image uniformly to transcode the image. For example, the encoding device may modify one or more quantization tables as a function of the near linear relationship between bitrate (R) and the number of zero-valued quantized transform coefficients to reduce the file size uniformly over the entire image. Alternatively, or additionally, the encoding device may transcode the image using bitrate control techniques that affect only specific localized regions of the image.

Abstract: Systems and methods of bad pixel cluster detection are disclosed. In a particular embodiment, a method includes determining a correlation value corresponding to a correlation coefficient between image data and at least one bad pixel cluster pattern, and detecting a bad pixel cluster corresponding to the at least one bad pixel cluster pattern based on the correlation value exceeding a threshold.

Abstract: The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line.

Abstract: Systems and methods of generating depth data using edge detection are disclosed. In a particular embodiment, first image data is received corresponding to a scene recorded by an image capture device at a first focus position at a first distance. Second image data is received corresponding to a second focus position at a second distance that is greater than the first distance. Edge detection generates first edge data corresponding to at least a first portion of the first image data and generates second edge data corresponding to at least a second portion of the second image data. The edge detection detects presence or absence of an edge at each location of the first portion and the second portion to identify each detected edge as a hard or soft edge. Depth data is generated based on the edge data generated for the first and second focus positions.

Abstract: In a particular embodiment, a method is disclosed that includes comparing a frame rate of image capture by an image sensor to a frame rate threshold at an image capture device. The method also includes when the frame rate is less than the frame rate threshold, increasing the frame rate to a modified frame rate that is greater than or at least equal to the frame rate threshold. The method further includes performing an autofocus operation on an image to be captured at the modified frame rate.

Abstract: Systems and methods to selectively combine video frame image data are disclosed. First image data corresponding to a first video frame and second image data corresponding to a second video frame are received from an image sensor. The second image data is adjusted by at least partially compensating for offsets between portions of the first image data with respect to corresponding portions of the second image data to produce adjusted second image data. Combined image data corresponding to a combined video frame is generated by performing a hierarchical combining operation on the first image data and the adjusted second image data.

Abstract: This disclosure describes an efficient architecture for an imaging device that supports image registration for still images and video coding of a video sequence. For image registration, the described architecture uses block-based comparisons of image blocks of a captured image relative to blocks of another reference image to support image registration on a block-by-block basis. For video coding, the described architecture uses block-based comparisons, e.g., to support for motion estimation and motion compensation. According to this disclosure, a common block comparison engine is used on a shared basis for both block-based image registration and block-based video coding. In this way, a hardware unit designed for block-based comparisons may be implemented so as to work in both the image registration process for still images and the video coding process for coding a video sequence.

Abstract: A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.

Abstract: This disclosure describes techniques for managing the clock speed of a bus during viewfinder mode in a digital camera device. The techniques involve determining a frame rate of frames displayed on a viewfinder, determining whether to adjust a clock speed of a bus based at least in part on the determined frame rate, wherein the bus is used to transfer the frames from a camera sensor to the viewfinder, and adjusting the clock speed of the bus upon determining that that the clock speed should be adjusted. The techniques may help ensure that the viewfinder delivers frames at a target frame rate. In addition, in some cases, the techniques may help to reduce power consumption by facilitating clock speed reductions in viewfinder mode.

Abstract: In a particular embodiment, a method is disclosed that includes illuminating an opaque mask having a plurality of holes formed therein, each hole of the plurality of holes having a predetermined size. The method includes forming a two-dimensional impulse response image of the illuminated opaque mask using a camera module. The method further includes determining at least one optical characteristic of the camera module based on the two-dimensional impulse response image of the illuminated opaque mask.

Abstract: A two-dimensional (2D) mesh is applied over a distortion surface to approximate a lens roll-off distortion pattern. The process to apply the 2D mesh distributes a plurality of grid points among the distortion pattern and sub-samples the distortion pattern to derive corrected digital gains at each grid location. Non-grid pixels underlying grid blocks having a grid point at each corner are adjusted based on the approximation of the lens roll-off for the grid points of the grid block. In one example, bilinear interpolation is used. The techniques universally correct lens roll-off distortion irregardless of the distortion pattern shape or type. The technique may also correct for green channel imbalance.

Abstract: This disclosure describes techniques of loading batch commands into a graphics processing unit (GPU). As described herein, a GPU driver for the GPU identifies one or more graphics processing objects to be used by the GPU in order to render a batch of graphics primitives. The GPU driver may insert indexes associated with the identified graphics processing objects into a batch command. The GPU driver may then issue the batch command to the GPU. The GPU may use the indexes in the batch command to retrieve the graphics processing objects from memory. After retrieving the graphics processing objects from memory, the GPU may use the graphics processing objects to render the batch of graphics primitives.

Abstract: An apparatus for detecting incursions for an aircraft and surface vehicles includes an incursion processor receiving ownship position from an ownship navigation processor, traffic information from a traffic surveillance processor, and obstacle information from an obstacle detector and generating alert information. The apparatus also includes a display processor receiving airport chart information and providing display information for displaying the alert information and airport chart information.