Abstract: The disclosed unbalanced-to-balanced signal converter circuit includes two pairs of transistors, each pair having first and second transistors with the base-to-emitter junctions of each pair being connected in series between a reference potential point and a constant current source. A driver circuit is arranged to supply an unbalanced input signal which increases the conductivities of the first transistor of the first pair and the second transistor of the second pair, while decreasing the conductivities of the second transistor of the first pair and the first transistor of the second pair, and vice versa. Balanced linear output signals are provided at the collectors of the second pair of transistors. A gain controlled amplifier and a capacitance control circuit each including the unbalanced-to-balanced converter are also disclosed.

Abstract: An analog subsystem is disclosed which can be included in a single monolithic, integrated circuit chip and which is for use with a digital subsystem to form a dual ramp analog-to-digital converter. A current steering network included in the analog subsystem is connected to a reference current source and to an input voltage-to-current converter. An integrator is connected to the output of the current steering network, and a comparator is connected to the output of the integrator. The current steering network selectively conducts the current from the converter to charge the integrator for a predetermined period of time, which is terminated by the application of a signal to the current steering network by the digital subsystem. The network then conducts the current from the constant reference current source to discharge the integrator which ultimately triggers the comparator.

Abstract: Frequency changing circuits are disclosed which each include an unbalanced input circuit, complementary mixing devices and a balanced output circuit. The mixer input signals are cancelled in the balanced output circuit. Moreover, whatever mixer out-of-phase output signals that are undesirably fed back to the input circuit are cancelled in the unbalanced input circuit. Also, circuitry is disclosed for rendering one or the other of the complementary mixing transistors inoperative so that the other of the complementary transistors can operate as a neutralized amplifier for utilization in a television receiver adapted to receive both VHF and UHF signals.

Abstract: An automatic hue control system operates to correct the phase of the color subcarrier reference signal used to operate the demodulators of a color television receiver. A regenerated color subcarrier signal at the phase of the I axis or the axis of flesh color is fed to one input of a phase comparator. The amplitude limited chrominance signal is fed to another input of the phase comparator, the output of which is used to operate a single pole double throw switch circuit. The switch passes the regenerated subcarrier signal to the demodulators when the phase difference between the limited chrominance and the regenerated subcarrier signals is outside a predetermined angle on each side of the I or flesh axis.

Abstract: An amplifier configuration is disclosed which utilizes a resistive, positive feedback network to develop a high input impedance. The amplifier, which is suitable for manufacture in monolithic integrated circuit form, includes a pair of differential transistors which are coupled to a current supply that provides a current having a predetermined temperature coefficient. A resistor, which is connected between the emitters of the differential transistors, develops either a temperature stable offset voltage or an offset voltage having a desired temperature coefficient in response to the current. A negative feedback circuit facilitates control of the bias voltages for the pair of differential transistors. Temperature stable quiescent input and output voltage levels are derived from the offset voltage through the feedback network.

Abstract: The frequency doubler includes circuits for charging and discharging a capacitor at a predetermined rate in response to each incoming cycle. First and second comparators are connected between the capacitor and the input of an OR gate. These comparators limit the magnitudes of the charged voltage and the discharged voltage of the capacitor. The OR gate responds to both comparators being off during a part of the rising portion of the capacitor waveform and during a part of the falling portion of the capacitor waveform by providing pulses having twice the repetition rate as the input pulses. An output circuit may be connected to the output terminal of the OR gate for converting the output signal of the OR gate into a further output signal comprised of current pulses having constant amplitude and duration.

Abstract: The driver circuit includes a differential amplifier, a double-to-single ended converter, an emitter follower amplifier and an output stage having one portion for driving one external complementary transistor and another portion for driving another complementary transistor. The driver output transistors of each portion of the output stage each has a biasing network including a semiconductor junction and a resistor which are driven by a constant current source. The bias networks enable the driver output transistors to provide quiescent currents of known magnitudes for biasing the complementary output transistors and to have high current gains so that the current source is able to supply a constant current of minimal magnitude. The biasing networks further provide temperature compensation of the driver output transistors. The driver output stage is suitable for being driven by a single ended drive signal.

Abstract: The amplifier configuration includes a double-to-single ended converter having two interconnected portions, each having three signal paths. Two of the signal paths include transistors of a first conductivity type having main electrodes coupled between one of the output terminals of a differential amplifier and a power supply conductor. The other path includes a transistor of the second conductivity type having a control electrode coupled to one of the differential amplifier output terminals and main electrodes coupled between power supply conductors. Identical current sources drive corresponding transistors of each portion. The transistors of the second conductivity type enable quiescent voltages of only one base-to-emitter voltage drop to be developed at each of the output terminals of a differential amplifier to facilitate balance and maximization of the dynamic signal range.

Abstract: The disclosed amplifier circuit includes a common base transistor, a turn-around device and a driver transistor, which is connected to a filter. An emitter follower stage is also connected to the filter. The turn-around device is connected between the common base and driver transistors. A diode connected transistor is utilized for compensating for the nonlinearity of the common base transistor. A first negative feedback path is provided between the driver and common base transistors to stabilize bias levels, increase amplifier output impedance and reduce distortion. A frequency compensation capacitor is connected to the driver transistor and a second negative feedback path is provided from the output of the emitter follower stage to the driver transistor. The second negative feedback path facilitates rapid discharge of the capacitor and driver transistor, a high slew rate and compensates for the nonlinearity of the emitter follower.

Abstract: A gain controlled audio amplifier for each channel which includes a differential to single ended converter fed by a differential amplifier, the common emitters of which are coupled to balance and volume control circuitry for controlling the amount of current flowing in the amplifier relative to the other three amplifiers. A pair of diodes are connected in back-to-back relationship between the control electrodes of the differential amplifier and receive a signal from an enhancement circuit which controls the amount of signal being applied to the input of the differential amplifier. The enhancement circuit includes a pair of amplifier sections which are connected together so that the output voltage of one increases as the other decreases and vice versa and the decrease of output voltage in either section occurs substantially more rapidly than the increase of output voltage in the other section.

Abstract: The disclosed protection circuit which is suitable for providing protection of transistors included in integrated circuits such as regulators and power amplifiers, includes thermal shutdown, safe area and current control circuits. The current control portion includes a sense transistor connected substantially in parallel with the transistor to be protected. In monolithic integrated circuit applications, the sense transistor has an emitter area that is a predetermined ratio of the emitter area of the protected transistor. A "sense resistor" is connected to the sense transistor and develops a control signal which is proportional to the instantaneous current being conducted by the protected transistor. A threshold circuit is coupled between the sense resistor and the drive circuit for the protected transistor and responds to the magnitude of the control signal crossing a predetermined threshold to remove or reduce the drive to the protected transistor.

Abstract: A tachometer for measuring and comparing the angular velocity of a first and a second wheel of a vehicle includes means for sensing and generating a train of pulses for each of the wheels wherein the repetition rates of the pulse train varies in proportion to the angular velocity of the wheel. For each of the wheels a frequency doubler is provided for doubling the repetition rate of the pulse train of the varying repetition rates having pulses of the same pulse width and amplitude. For each wheel the frequency doubled pulse train is then integrated to provide a DC output. The two DC outputs for the two wheels are then compared, selected and applied to corresponding output terminals of the tachometer.

Abstract: A silicon monolithic integrated circuit color television demodulator includes three sets of full-wave synchronous switched demodulators for demodulating the red, blue and green color signals or color difference signal present in a composite television signal. Each of the demodulators consists of two pairs of switching transistors, and the transistors in each of the pairs are rendered alternately conductive by reference signals derived from a reference oscillator in a color television receiver. Signals from the reference oscillator at the phases of +(R-Y) and -(B-Y) color difference signals are applied to the red and blue demodulators, respectively. The reference signal for the green demodulator is obtained by applying the +(R-Y) reference signal to one transistor of each of the two pairs of switching transistors in the green demodulator and by applying a portion of the -(B-Y) reference signal to the other transistor in each of the pairs.

Abstract: The disclosed amplifier has a simple structure which is particularly suited for integrated circuit applications. The amplifier includes a differential amplifier having first and second input terminals across which an input signal is developed. Diodes are connected from each of the input terminals to a circuit node. A reference signal is coupled to the input terminals of the differential amplifier and hence to the diodes. A gain control transistor is connected between the circuit node and ground. The conductance of the gain control transistor varies in response to a gain control signal to thereby control the conductance of the diodes. As the conductances of the diodes increase, less of the input signal voltage is developed across the diodes and hence the gain is decreased and vice versa. The d.c. output voltage remains constant even though the gain is changed.

Abstract: The disclosed methods and systems provide a variety of 38 kilohertz signals suitable for use with various stereo decoding circuits. The methods relate to the generation of reference and related rectangular waves and the combination thereof to remove the third harmonic component from the resulting multi-level decoding signal. The disclosed decoding signal generator system structure includes an oscillator, a shift register and a single combiner. The oscillator provides an output signal which is a predetermined multiple of the stereo decoding signal. The shift register derives frequency divided and phase shifted signals from the output signal of the oscillator and the signal combiner to form the stereo decoding signal.

Abstract: A current limit circuit is disclosed for sensing the current drain of a load connected in series therewith. Under normal operating conditions the circuit presents a relatively low impedance in series with the load. Circuit overload protection is provided if the current increases above a predetermined value by a current limiting circuit provided for limiting the current conducted therethrough. In response to the current limiting condition, thermal shutdown of the circuit occurs to reduce the current that is supplied to the load to a predetermined minimum value i.e., the current limit circuit presents an impedance to the load which is relatively much greater than the impedance of the current limit circuit during normal operating conditions. After a predetermined time, the current limit circuit is again rendered operative and if the circuit overload condition is still present the aforedescribed cycle is repeated until the fault condition is corrected.

Abstract: A stabilizing circuit which increases the effective value of a capacitor and the structure of a monolithic capacitor are disclosed. The stabilizing circuit includes a transistor having a base electrode connected to the capacitor and an emitter electrode connected to a point at which it is desired to provide an increased effective capacitance. The capacitor structure is suitable for being included in monolithic integrated circuits having diffused isolation regions. A first plate of the capacitor is formed by a metallization layer, the second plate of the capacitor may be formed by an emitter diffusion into the isolation diffusion. A base diffusion which is conductively connected to the emitter diffusion and to the isolation diffusion facilitates connection of the second plate of the capacitor to the substrate.

Abstract: A shell eyelet axial lead header for a planar contact semiconductive device is disclosed wherein a series of bonding pads are first formed as part of a lead frame. The bonding pads are in a planar configuration, are supported by small breakable tabs from a surrounding ring and when the ring is broken away, the tabs are isolated from each other.A shell eyelet, a glass preform with lead holes therethrough, leads with braze material attached at one end and a lead frame with bonding pads attached are assembled in an appropriate manner and passed through a furnace. The glass melts and bonds to the leads, to the shell eyelet and to the bonding pads. The lead braze melts and bonds the leads to the bonding pads. After cooling the supporting ring of the bonding pads is broken away to leave the isolated bonding pads and the finished device.If the bonding pads are not sufficiently planar so as to receive the beams of a beam lead device, the bonding pads may be lapped to flatness.

Abstract: The disclosed junction field-effect transistor (FET) has a precisely controlled gate configuration which enables either high power operation or high frequency operation or both. The FET is manufactured by steps including the growing of a first epitaxial layer having a predetermined crystallographic orientation on a substrate to form a drain. Next, a first anisotropic etch of the epitaxial layer provides "U"-shaped grooves with flat bottoms, therein through which a gate is diffused having internal side walls of uniform depth that define the source-to-drain channel. A second epitaxial layer is then grown on the surface of the first epitaxial layer and of the gate to provide a source. A second anisotropic etch exposes a portion of the gate, which also forms an etch stop, to facilitate electrical contact thereto. Current flowing through the channel is controlled in response to an input signal applied between the gate and source which adjusts the thickness of a depletion region extending into the channel.

Abstract: A gain controlled audio amplifier for each channel which includes a differential to single ended converter fed by a differential amplifier, the common emitters of which are coupled to balance and volume control circuitry for controlling the amount of current flowing in the amplifier relative to the other three amplifiers. A pair of diodes are connected in back-to-back relationship between the control electrodes of the differential amplifier and receive a signal from an enhancement circuit which controls the amount of signal being applied to the input of the differential amplifier. The enhancement circuit includes a pair of amplifier sections which are connected together so that the output voltage of one increases as the other decreases and vice versa and the decrease of output voltage in either section occurs substantially more rapidly than the increase of output voltage in the other section.