Abstract: An orthogonal frequency division multiplexed wideband communication system provides improved time and frequency synchronization by inserting an unevenly spaced pilot sequence within the constellation data. A receive correlates the received data using the unevenly spaced pilot sequence. The pilot sequence is generated with a maximum length pseudo random noise code and inserted into frequency bins having prime numbers.

Abstract: A driver circuit (33) for output buffers or the like provides differing switching speed and di/dt depending on whether an output signal is switched in response to input signals or a control signal.

Abstract: A current driver circuit (10) sources current to an output node (N4) in response to an input signal (VI) being a logic high. The current driver circuit (10) utilizes a current source (16) which sinks current from the output node (N4) in response to the input signal (VI) switching from a logic high to a logic low. The current source (16) is deactivated for a predetermined time delay after the input signal (Vi) switches from a logic high to a logic low.

Abstract: A bandgap voltage reference circuit (50, 100) which operates at low power supply voltages provides a reference current as either a one- or a two-.DELTA.V.sub.BE voltage across a first resistor (82, 133). A current proportional to the reference current is mirrored into one terminal of a second resistor (94, 133) to provide the bandgap voltage. Compensation for base currents injected into the circuit (50, 100) by two transistors forming the .DELTA.V.sub.BE reference is provided. In one embodiment (50), base currents of first (66) and second (87) transistors which have equal emitter areas and collector current density as the two transistors (68, 85) forming the .DELTA.V.sub.BE reference compensate for the injected base currents. In another embodiment (100), a single transistor (127) injects current substantially equal to the sum of the base currents of the two transistors (116, 121) forming the .DELTA.V.sub.BE reference.

Abstract: An apparatus for performing multiplications with reduced power includes an arithmetic logic unit and a decode block for performing an equivalent of a multiply instruction. A frequently-encountered multiply instruction occurs between a variable and a known constant. If the known constant is positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to zero, or subtract the variable from zero, in response to the sign bit of the known constant. In response to a multiply and accumulate instruction between a variable and a known constant of positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to the prior accumulated result or to subtract it therefrom, in response to the sign bit of the known constant. In either case, the high-speed multiplier is disabled and its power saved.

Abstract: A dynamic random access memory includes memory cells located at intersections of word lines and differential bit line pairs. A row decoder activates a word line in response to a row address. A first sense amplifier coupled to each bit line pair then increases the small differential voltage of the bit line pair to positive and negative power supply voltages. The first sense amplifier is then isolated from the bit lines so that the bit lines may be equalized. The contents of memory cells along the activated word line are stored in corresponding first sense amplifiers, and the memory functions as a by-one static random access memory during successive page-mode cycles. At the end of the page-mode cycles, the first sense amplifiers are recoupled to the bit lines, and second sense amplifiers update modified data and refresh the charge stored in the memory cells.

Abstract: An electrical contact (46) to a phosphorous doped polysilicon gate electrode (18) is formed by preventing arsenic, from a source and drain implant, from doping a portion (22) of the polysilicon gate electrode (18). A photoresist mask (20) covers a portion (22) of the polysilicon gate electrode (18) during the implant, thus preventing it from being doped. An electrical contact (46) is then formed to the masked portion (22) of the polysilicon gate electrode (18).

Abstract: A sigma-delta digital-to-analog converter (20) reduces even order distortion, such as a DC offset, in an output signal by chopping the output signal alternately with set and reset pulses. The sigma-delta digital-to-analog converter (20) includes a sigma-delta modulator (25), a chop circuit (261) associated with a corresponding bit of the sigma-delta modulator (25), and an output buffer (264) for providing the output signal. The chop circuit (261) alternately inserts first and second logic levels into an output data stream of the sigma-delta modulator (25) before providing it to the output buffer (264). Even-order distortion is eliminated with only a tolerable attenuation of the output signal.

Abstract: A continuous-time differential amplifier (52, 100) preserves fast settling time while reducing a relatively-high offset voltage-normally associated with a continuous-time differential amplifier using MOS load transistors. The differential amplifier (52, 100) includes a first transistor (81) biased as a current source to provide current into emitters of second (82) and third (83) emitter-coupled input transistors. Fourth (84) and fifth (85) load transistors are respectively coupled between collectors of the second (82) and third (83) input transistors and a power supply voltage terminal. An amplifier (70) having a positive input terminal coupled to the collector of the second input transistor (82) and a negative input terminal receiving a bias voltage biases the control electrodes of the load transistors (84, 85). The amplifier (70) increases the effective transconductance of the load transistors (84, 85) to allow larger control electrode areas, which reduces the effect of transistor mismatch.

Abstract: A tuning circuit (30) provides selection signals to a passive component array (80) in a continuous-time filter (70) to compensate for wide variations in values which are encountered in integrated circuit processing. The tuning circuit (30) includes at least one capacitor (46) and at least one resistor (31), and a plurality of either capacitors or resistors. A largest component is enabled and an integration of a reference current during a predetermined period is performed. If the integration provides a voltage greater than a reference voltage, then a corresponding selection signal is set and the component is selected. Successive integrations are performed to determine which components are enabled by corresponding selection signals in order to enable a combination of components which most closely integrates the reference current to the reference voltage. When selection signals corresponding to all components have been determined, the selection signals are applied to corresponding components in the filter (70).

Abstract: An improved LDD CMOS fabrication is disclosed which uses a reduced number of processing steps. In accordance with one embodiment of the invention, a silicon substrate is provided which has first and second surface regions of opposite conductivity type. First and second silicon gate electrodes overlie the first and second surface regions, respectively. A dopant source layer containing dopant impurities of the first conductivity type is deposited over the first and second gate electrodes. This dopant source layer is patterned to form sidewall spacers at the edges of the first silicon gate electrode. Those sidewall spacers are used in the formation of the LDD structure on the devices formed in the first surface region. After removing the sidewall spacers, the structure is heated to diffuse dopant impurities from the dopant source layer into the second surface region to form source and drain regions of transistors formed in that region.