Abstract: A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.

Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

Abstract: A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay.

Abstract: Level shifting circuits and methods are disclosed. One embodiment provides a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. One embodiment includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor (“NMOS”) cascode circuit, the second driver includes a p-channel metal oxide semiconductor (“PMOS”) cascode circuit, and the output driver includes a complementary metal oxide conductor (“CMOS”) inverter stage.

Abstract: A clearinghouse authorizes a content provider to use a scrambler to scramble content using a content ID. The content provider provides the scrambled content to a content consumer. If the content consumer has a valid authorization, it can use a content descrambler and the content ID to descramble and access the content. Authorization takes the form of a electronically signed authority message including a device ID and the content ID. The authorization is valid for the content consumer if the device ID matches a corresponding value in the descrambler. The scrambler implements an irreducible scrambling function that can be performed quickly in special-purpose hardware but not on general purpose hardware or software. The scrambler and descrambler can also be used to authenticate the content consumer.