Abstract: The next generation digital signal processors and reduced instruction set chip processors have multiple arithmetic and logic units and multiply and accumulate units to boost the processor performance. This technique along with higher clock speed of the processors has moved the processor throughput bottle neck to the bus bandwidth. Thus, a bandwidth efficient implementation of standard processing functions is very important to improve the real throughput of these processors. A few processors already use a wide data bus to access multiple consecutive data elements in memory to boost the bus bandwidth. This feature has been used extensively to speed up the cache performance. Disclosed herein is a bandwidth efficient implementation of FIR filter. In any intensive signal processing applications, filters are the basic processing function. The proposed method reduces the required bus bandwidth by about a factor of 2.7 without increasing the number of MAC operations.

Abstract: A duty cycle controller provides a uniform 50% duty cycle in a 2:1 digital multiplexer without an upper operating frequency limit. The multiplexer uses a comparator to generate interleaving signals by comparing a clock signal to a comparator set point. A feedback loop includes a bandpass filter, a power detector and an integrator, connected in series between the multiplexer output and the comparator. The bandpass filter passes components of the multiplexed output signal with a frequency substantially equal to the main clock frequency of the multiplexer. Signal components at that frequency are a second harmonic of the fundamental frequency of the multiplexed signal and therefore will not be present in the multiplexed signal if its duty cycle is exactly 50%. The power level of those frequency components is integrated over a suitable time period and the integrated signal is used to adjust the set point of the comparator.

Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

Abstract: A technique for regulating a DC source voltage extracts charge from a capacitor to maintain a fixed voltage across an output load, the voltage across the output load being smaller than the DC source voltage. An output voltage that indicates a voltage drop across the capacitor is sensed and compared to a voltage reference source. The on-time of a switch, connected in series with a transformer, the series combination connected across the capacitor, is varied based on the result of the comparison, thereby controlling the voltage across the capacitor and the output voltage.

Abstract: Higher write speeds in hard disk write preamplifiers require higher supply voltages. The voltage across an inductive write head, VL, is proportional to the value of inductance, L, and to the speed at which the write current is reversed, di/dt. Accordingly, the write current reversal time in inductive write-heads fundamentally depends on how large a voltage can be impressed across the write drive head. The proposed circuitry and method provides a voltage boost circuit for hard disk drive preamplifiers that satisfies the demand for improved rise-time while meeting the conflicting demand for maintaining a same supply voltage.

Abstract: An oscillator is formed using a Field-Effect Transistor (FET) in a Colpitts configuration. The circuit has a resistor from source to ground. Also connected to the source are two capacitors, one between the source and ground while the other is from source to gate. These capacitors provide a phase-shifted feedback signal to the gate. Also connected to the gate is the varactor tank, which has a voltage variable reactance that is used to tune the oscillation to the desired frequency. Between the drain of the FET and the supply voltage is a resistor-capacitor network. Between two series resistors a shunt capacitor is added to minimize local oscillator leakage onto the Vdd line. The resistor network also provides impedance for the Pre-Scalar output, which is simply a connection to the drain of the FET. The pre-scalar output is used to provide a reference signal to the phase-locked loop, which generates the correction voltage to the oscillator's VCO input.

Abstract: A process for recycling a reaction system of electroplating passivation of wafers, in which lanthanum hydroxide (La(OH)3) or magnesium hydroxide (Mg(OH)2) is added to supplement the lanthanum ion or magnesium ion consumed in an electroplating solution when the pH of the electroplating solution decreases to a range from 0.1 to 0.4.

Abstract: A hard disk drive write channel architecture improves the rise-time while utilizing a same supply voltage to provide a boosted voltage, thereby improving the rise-time only when it is needed. The voltage is then connected to the inductive write head through a switch after an appropriate delay, so as to compensate for the delay between the switching of Data line and the peaking of the voltage at the corresponding write terminal. In addition, the same delayed version of the Data line is applied to the inputs of the switching circuit to delay the signal inputs such that the delay timing matches appropriately.

Abstract: A wireless remote data sensor is disclosed for use in the cable television industry. It senses the status of equipment in the field, such as battery backup power equipment, amplifiers, pilot and signal level monitors, and voltage level for powering active equipment, and transmits the status information using a low data rate cellular data service known as Cellemetry. It also allows the cable system operator to switch each power supply to a backup power source and back remotely for conditioning and battery capacity measurement. Cellemetry uses the forward and reverse control channels of the AMPS cellular network to communicate 32 bit data packets.

Abstract: A secure electronic monetary transaction system (SEMTS) provides absolute security for electronic financial transactions. These transactions can be of any kind provided they are numeric in content and of known length. The SEMTS encrypts and decrypts source numeric data using a private, numeric key known only by both parties in the transaction. The secure distribution of these keys will be under the same methods that the financial institutions use to distribute the original source data such as credit cards, account numbers, etc. The system uses nine simple, open formulas for translating source numbers into encrypted cipher numbers. These formulas return every possible value, except the input value, and are completely dependent on the key. Because there are no hidden parts, the architecture of the SEMTS is completely available to anyone in the public sector. This open architecture makes stealing the cipher numbers worthless. The only way to break a number is to know the key.

Abstract: A crossing network that matches buy and sell orders based upon a satisfaction and quantity profile is disclosed. The crossing network includes a number of trader terminals that can be used for entering orders. The orders are entered in the form of a satisfaction density profile that represents a degree of satisfaction to trade a particular instrument at various (price, quantity) combinations. Typically, each order is either a buy order or a sell order. The trader terminals are coupled to a matching controller computer. The matching controller computer can receive as input the satisfaction density profiles entered at each one of the trading terminals. The matching controller computer matches orders (as represented by each trader's satisfaction density profile) so that each trader is assured that the overall outcome of the process (in terms of average price and size of fill) has maximized the mutual satisfaction of all traders. Typically, the matching process is anonymous.

Abstract: A secure electronic messaging system (SEMS) provides absolute system security and user-defined message security for electronic messaging between two public entities. These messages can be of any kind provided the contents are created using a defined master alphabet of 81 characters or less. The SEMS encrypts and decrypts source message data using a series of message keys that are derived from a private, numeric original key known only by both parties sending and receiving messages. The message key suite absolutely secures the original key from discovery. The secure distribution of these original keys will be under the same methods that the public entities would use to discover each other such as opening an account, making a public inquiry for membership, etc. The system is based on the simple mathematics for secure electronic monetary transactions that translates source numbers into encrypted cipher numbers.