Abstract: The present invention relates to a solid electrolytic capacitor having a large capacitance and a higher resistance to heat and adapted as a surface-mount device and a method of producing the same. The invention may include the followings features: (1) a layer containing an electroconductive polymer and a less conductive polymer is provided on a dielectric oxide film on the positive electrode foil; (2) a separator of a polyester resin based unwoven fabric made by span bonding and/or wet processing a resin material is sandwiched between the positive electrode foil and the negative electrode foil and rolled together to form a capacitor element which also include a solid electrolyte; (3) a separator is sandwiched between the positive electrode foil and the negative electrode foil coated with a dielectric oxide film exhibiting a withstand voltage of 0.

Abstract: A VLIW processor includes a plurality of containers holding a plurality of sub-instructions in a VLIW instruction, an exchanging portion exchanging the plurality of sub-instructions held in the plurality of containers and inputting the instructions to the plurality of containers, a plurality of decoders decoding the sub-instructions held in the plurality of containers, and a plurality of processing units executing the sub-instructions decoded by the plurality of decoders. Since the exchanging portion exchanges a plurality of sub-instructions held in the plurality of containers and inputs the instructions to the plurality of containers, a compressed code can be executed in such an execution sequence that is taken prior to compression.

Abstract: An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

Abstract: A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time.

Abstract: A development system that contains a developer carrier for carrying a developer on the surface thereof to a development region opposite to an image bearing body, and a regulating member biased into contact with the surface of the developer carrier by a predetermined pressure for regulating an amount of developer carried by a developer transport member. The developer carrier has a surface coated with fine particles with an average particles size of between 3 and 30 .mu.m which are bonded with the surface.

Abstract: An arrangement for monitoring operations of advanced intelligent network (AIN) elements of a public switched telephone network by transporting standardized network management messages across a data network. A maintenance and operations console (MOC) sends and receives Simplified Network Management Protocol (SNMP) objects from AIN elements such as an Intelligent Peripheral (IP) via a packet switched network using a standardized transport protocol such as TCP/IP. The IP includes an error monitoring system that collects error messages and generates an error status report. An SNMP agent internal to the IP converts the error status report to SNMP objects outputs the SNMP objects onto the packet switched network. The HOC receives the SNMP objects, assigns an operational priority to the SNMP objects, and displays the operational priority of the received SNMP objects based on object relationships identified by a Management Information Base (MIB).