Abstract: A robotic bending apparatus for bending archwires and other types of elongate, bendable medical devices into a desired configuration includes a first gripping tool and a moveable gripping tool. The first gripping tool can be either fixed with respect to a base or table for the robot or positioned at the end of robot am. The moveable gripping tool is mounted to the end of a moveable robot arm having a proximal portion also mounted to the base. The robot preferably comprises a six axis bending robot, in which the distal end of the moveable arm can move relative to the fixed gripping tool about three translational axes and three rotational axes. The gripping tools preferably incorporate force sensors which are used to determine overbends needed to get the desired final shape of the archwire. The robot may also include a resistive heating system in which current flows through the wire while the wire is held in a bent condition to heat the wire and thereby retain the bent shape of the wire.
Type:
Grant
Filed:
September 14, 2007
Date of Patent:
December 27, 2011
Assignee:
Orametrix, Inc.
Inventors:
Werner Butscher, Friedrich Riemeier, Rüdger Rubbert, Thomas Weise, Rohit Sachdeva
Abstract: A method and system for reducing glitch effects in combinational logic is presented. If combinational logic incurs a particle-induced single event transient (SET) signal, a glitch reducing circuit, which is connected in a signal path between the combinational logic and downstream logic, will prevent the SET from propagating to the downstream logic. The glitch reducing circuit functions as a signal filter that provides a SET-filtered drive signal to downstream logic. The glitch reducing circuit receives both the input to the combinational logic and the output from the combinational logic. The input acts to enable or disable the glitch reducing circuit, so that for certain input values, the glitch reducing circuit passes the logic output signal to downstream logic, and for other input values, the glitch reducing circuit blocks the output signal from passing to downstream logic.