Abstract: A system for mounting a hard disk enclosure (HDE), includes a casing pivotably mounted to minimize at least one of settle-out dynamics, external rotational vibration, and emitted vibration, the casing allowing the HDE to rotate substantially freely, wherein the center of gravity of the HDE is substantially the same as a pivot point of the casing. Further, a computer chassis includes a housing, at least one disk drive assembly for being housed by the housing, and a plurality of theta-mounts integrally built within the housing.
Type:
Grant
Filed:
September 3, 2003
Date of Patent:
August 30, 2005
Assignee:
Hitachi Global Storage Technologies Netherlands B.V.
Inventors:
Sri M. Sri-Jayantha, Vijayeshwar Das Khanna, Gerard McVicker, Hien Dang, Arun Sharma, Kiyoshi Satoh, Tatsuo Nakamoto
Abstract: A disk drive (HDD) (and method) subject to linear and rotational vibration, includes an independent sensing unit for sensing a rotational velocity component of the rotational vibration in a predetermined frequency range, and an optimal filter combination for receiving an output from the sensing unit.
Type:
Grant
Filed:
May 24, 2002
Date of Patent:
May 24, 2005
Assignee:
Hitachi Global Storage Technologies Netherlands B.V.
Inventors:
Sri M. Sri-Jayantha, Hien Dang, Arun Sharma, Isao Yoneda
Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.
Type:
Grant
Filed:
June 12, 2001
Date of Patent:
July 6, 2004
Assignee:
International Business Machines Corporation
Inventors:
John E. Campbell, William T. Devine, Kris V. Srikrishnan
Abstract: A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.
Type:
Grant
Filed:
February 25, 1999
Date of Patent:
September 3, 2002
Assignee:
International Business Machines Corporation
Inventors:
Ramachandra Divakaruni, Yujun Li, Jack A. Mandelman
Abstract: A semiconductor structure is provided along with a corresponding method of producing such a structure. The method and structure may include providing a semiconductor substrate, a gate insulator over the semiconductor substrate, a conductor comprising intrinsic polysilicon over the gate insulator, a silicide layer over the polysilicon and an insulating cap over the silicide layer. Insulating spacers may be provided along sides of the silicide layer and the insulating cap. The polysilicon may be doped with a first conductive type dopant. The first conductive type dopant may be spread over the polysilicon to form a doped polysilicon layer. A gate sidewall layer may be formed on sides of the doped polysilicon layer. A bird's beak of the gate sidewall layer may also be formed in a corner of the polysilicon.
Type:
Grant
Filed:
October 22, 2001
Date of Patent:
August 13, 2002
Assignee:
International Business Machines Corporation
Inventors:
Jack A. Mandelman, Ramachandra Divakaruni
Abstract: A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET). The method forms an insulator layer over a substrate and a doped layer over the insulator layer. Further, the invention patterns a conductor layer over the doped layer. The conductor layer includes gate conductors. The invention implants a second impurity through the conductor layer and into the doped layer. The second impurity is of an opposite type than that of the first type of impurity. Also, the second impurity decreases the effective concentration of the first impurity in the doped layer. The amount of the second type of impurity that penetrates through the conductor layer into the doped layer changes depending upon the length of the gate conductors within the conductor layer.
Type:
Grant
Filed:
June 6, 2001
Date of Patent:
August 13, 2002
Assignee:
International Business Machines Corporation