Patents Represented by Attorney McGinn Law Group, PLLC
  • Patent number: 8237287
    Abstract: A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Tada, Tsuyoshi Hirakawa, Hironori Nakamura, Takayuki Kurokawa
  • Patent number: 7443687
    Abstract: A heat sink mounting device according to the present invention can secure a mounting space of the heat sink sufficiently, mount a heat sink with large capacity, and use a main board in common even when a dual central processing unit (CPU) is constituted by extension of CPU. A main board has an opening. A CPU is mounted on a main surface of the main board. A sub board is attached on the main surface of the main board to permit the opening to be covered. An extension CPU is mounted on the sub board through the opening from a rear face side of the main board. A first heat sink is mounted in the main surface side of the main board to permit the CPU and the opening to be covered. A second heat sink is mounted in the rear face side of the main board to permit the extension CPU and the opening to be covered.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: October 28, 2008
    Assignee: NEC Corporation
    Inventor: Koichi Fujioka
  • Patent number: 7171590
    Abstract: A multi-processor system includes a partition including a selected number of nodes selected from a plurality of nodes provided in a plurality of node groups, each of the nodes including a computer. A failed node in the partition notifies a failure to a corresponding service processor of the node group and other nodes of the partition. The corresponding service processor and the service processors managing the other nodes notify the error log information to a service processor manager, which identifies the location of the failure and indicate the service processors to recover from the failure.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: January 30, 2007
    Assignee: NEC Corporation
    Inventor: Tadashige Kadoi