Abstract: A semiconductor integrated circuit having a standard pair of complementary data lines subjected to ternary control, through which data complementary to each other are transmitted when valid data are transmitted, single data lines subjected to binary control, through which data of the same system as that of the pair of complementary data lines are transmitted and a circuit for detecting valid data in a standard intermediate latch circuit which detects an event that the data transmitted through the standard pair of complementary data lines are changed to data complementary to each other, wherein the circuit for detecting valid data confirms arrival of the valid data and controls data corresponding to the data transmitted through the single data lines, to thereby reduce the number of pairs of data lines for narrowing an wiring area of the data lines and reducing a chip size while maintaining a high speed operation.