Abstract: A process and system for attaining a desired braking value is disclosed. The actual braking value is adjusted until the desired braking value is attained. Conventionally the braking hysteresis worsens the response of a brake and, thereby, worsens the quality of the regulation of a braking system with regulated braking value. Known processes reduce the brake application energy in steps if the actual braking value is too great until the braking hysteresis has been overcome and the desired braking value has been attained. Whereas, the present invention decreases the brake application energy ZS by a value (HyS+W) consisting of the braking hysteresis HyS associated with the desired braking value and a effect drop-off W. This decrease occurs in the case of excessive actual braking value BI. The process accelerates the attainment of the desired braking value BS. The preferred area of application for the invention are braking systems in the automotive industry.

Abstract: A dual photo-resist process for fabricating capacitor plates of a DRAM is disclosed including the step of forming a capacitor on a semiconductor IC surface. A first plurality of photo-resist regions which are separated from each other by spaces are then formed on the capacitor plate layer. At least one second photo-resist region is then formed on the capacitor plate layer which partially fills a space between, and is adjacent to one of, two of the first photo-resist regions. The capacitor plate layer is then etched below the spaces between the first and second photo-resist regions to form a plurality of individual capacitor plates including one capacitor plate for each DRAM cell.

Abstract: A MOST capacitor for use in a DRAM cell is formed by depositing a conductive polysilicon electrode layer on the substrate. Oxide lines are then formed on the polysilicon layer. Using the oxide lines as a mask, pillars are etched in the polysilicon electrode layer.

Abstract: A transpose memory is disclosed which has four dual port memories, a first counter for writing elements in the dual port memories and a second counter for reading out elements from the dual port memories. If the received matrix is to be outputted to the first type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element. If the received matrix is to be outputted to the second type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the "evenness" or "oddness" (i.e., divisibleness by two) of the row and column of the matrix element.

Abstract: A logical operation method for evaluating a train of output data to be obtained when a plurality of input patterns are successively applied to a memory element whose output value depends upon a sequence of input values. For each of the plurality of patterns in time series, the method decides whether or not the pertinent pattern is a holding pattern which means that the output value of the memory element depends upon a preceding pattern. Subsequently, the method evaluates a first train of data which consists of flags each indicating whether or not the respective pattern is the holding pattern, and a second train of data which consist of a predetermined logical values for the holding patterns and output logical values of the memory element for the non-holding patterns. Finally, the method subjects the first and second trains of data to operations in parallel by the use of a parallel arithmetic unit, thereby obtaining the train of output data of the memory element in parallel.