Abstract: A pressure medium actuated braking system comprises at least first and second braking circuits, and a multi-circuit braking power imparting device, such as a motorcar brake valve. The first braking circuit assigned to, e.g., the rear axle, has a first pressure medium storage container, at least one braking cylinder, and a first control valve system which connects the braking cylinder to the first pressure medium storage container or to a pressure medium sink (atmosphere) depending on a first control signal produced by the motorcar brake valve. The second braking circuit, assigned to, e.g., the front axle, has a second pressure medium storage container, first and second braking cylinders, and a second control valve system which connects the first and second braking cylinders to the second pressure medium storage container or to a pressure medium sink depending on a second control signal generated by the motorcar brake valve.

Abstract: A communication network and process for communicating thereon is disclosed which can support multimedia communications. Communication channels are formulated using a two step process. In a first step, channel types and fixed attributes thereof are defined. When needed, one or more channels of the predefined types are subsequently allocated in a second step wherein user-definable parameters are specified. The user-definable parameters and fixed attributes of each allocated channel control the scheduling of transmission and receipt of information on each channel.

Abstract: A level shifting inverter is provided with first and second drivers which may be level shifting inverters, which each have a low enable input, a high enable input and an output. Each driver outputs a low voltage level or a second high voltage level(that is higher than a first high voltage level of an input signal) depending on enabling and disabling voltage levels received at the high and low enable inputs of each driver. The high enable input of the first and second drivers are connected in a cross-coupled feedback configuration. The input of the first driver receives a complement of the input signal whereas the input of the second driver receives the input signal. The level shifter also has transition driver circuitry. The transition driver circuitry has an input receiving the second high voltage level, a first biasing input receiving the input signal and a second biasing input receiving the complement of the input signal.

Abstract: Multicast video services are provided in a network having a star topology. The network illustratively compromises a switched hub having a shared transmission medium and a plurality of ports. An Ethernet segment is connected to each port. Client stations belonging to the Ethernet segments communicate to the associated ports information identifying the particular multicasts they wish to receive. This is accomplished by sending special packets (mask update packets) from the client stations to the ports. Only multicast video data packets belonging to multicasts identified in the update packets are transmitted by the ports on the associated Ethernet segments.

Abstract: A process for the manufacture of pharmaceutical grade ranitidine base(N-?2-???5-(Dimethylamino)methyl!-2-furanyl!methyl!thio!ethyl-N'-methy l-2-nitro-1, 1-ethenediamine), is described. In-vitro and in-vivo pharmacological studies and acute toxicity studies indicate that it is as active and as safe as Form 2 ranitidine hydrochloride.

Abstract: The invention relates to a time display apparatus consisting of at least two partly transparent discs (A, B, C) which are arranged concentrically and axially displaced with respect to one another, with each of the discs (A, B, C) being rotationally driven about the central axle with separately preselectable period duration and being provided with a visible marking for the display of hours, minutes and seconds, with one freely rotating disc (D, E) which carries a graphical representation being concentrically arranged axially adjacent to at least one of the rotationally driven discs (C). The invention is based on the object of displaying not only the time by means of the time display apparatus, but also of enabling special optical effects. This is achieved in such a way that the rotationally driven disc (C) is provided with a (first) entrainment means (X.sub.1) on its side facing the freely rotatable disc, which means cooperates with a (first) actuating means (X.sub.

Abstract: An SC-integrator comprises an amplifier connected to a circuit network, which includes an integrating capacitor and a storage capacitor. The storage capacitor is connected via a first switch to the output of the amplifier and via a second switch directly to one side of a switching circuit capacitor, which is also connected by means of third and fourth switches to ground and the inverting input of the amplifier, respectively. The other side of the switching circuit capacitor is connected by means of a fifth switch to an input voltage Vin, via a sixth switch to ground, and by means of a seventh switch to a reference voltage Vref. The SC integrator uses a storage capacitor of relatively low capacitance value, since the storage capacitor is connected in parallel with the switching circuit capacitor when effecting a reversal of the voltage polarity across the integrating capacitor.

Abstract: A drive apparatus for reversible movements of an actuator is provided with a drive element made from a shape memory alloy with one-way effect. The drive element acts upon a lever rotatable about an axle in opposition to the force of a resetting element, wherein the lever can be used as a coupling member for converting a deformation of the drive element into a movement of the actuator. The drive element is a winding with a plurality of turns of a wire, wherein the turns are fixed and arranged mechanically parallel between an anchor point and the lever so that the lever is rotatable about the axle by means of a deformation of a turn, and the tractive force acting upon the lever by means of the drive element results from the individual forces of the turns of the winding acting mechanically parallel upon the lever. The diameter of the wire is advantageously approximately equal to the standardised diameter of the crystalline grain of the shape memory alloy in the austenitic state.

Abstract: A display device with article support device thereon is provided. The article support device is elongatable to cope with different size of the article. The display device has a casing which defines an inside which is space within the casing and an outside which is space not within the casing. The display device comprises a rear casing having two passages. The support device comprises an elongatable frame and a retainer which passes through the passage and is connected to the rear casing by a first screw. The retainer has a first end on which a pressure exertion apparatus is provided. The pressure exertion apparatus is accessible from outside. A thread is provided at the pressure exertion apparatus and cooperates with a second screw. The retainer and the second screw have a hole for passage of the elongatable frame which is positioned and unable to move when the second screw is screwed to tighten the pressure exertion apparatus.

Abstract: A phase-locked-loop (PLL) has a current controlled oscillator (ICO) whose gain varies with its input current. The PLL also contains a charge pump that controls the input current of the ICO and therefore the output frequency of the ICO. The charge pump has a gain that is controlled by the ICO input current in a manner which linearizes the combination of charge pump and ICO. This results in a substantially constant loop gain for a PLL.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder. The rate control has embodiments useful for constant bit rate and variable bit rate encoding of video frames. The present invention relates to statistical multiplexing, virtual buffers and virtual buffer verifiers.

Abstract: An apparatus and method for demodulating a frequency-shift keyed (FSK) signal to provide a data signal. An input FSK signal is processed in a waveform reshaper to generate a first pulse signal which includes a pulse for each cycle of the FSK signal. The first pulse signal is processed in a cycle counter to generate second and third pulse signals. The second pulse signal includes a pulse for each time a low clock pulse count is reached between pulses of the first pulse signal, and the third pulse signal includes a pulse for each time a high clock pulse count is reached between pulses of the first pulse signal. The low and high pulse counts are generally indicative of cycles of first and second FSK carrier frequencies, respectively, in the input FSK signal. The second pulse signal is processed in a data recognizer to generate a logic level indicator signal.

Abstract: An arrangement for interconnecting groups of users into collision domains in a Local Area Network such as an Ethernet comprises a plurality of repeater groups, with each repeater group being connected to a group of user stations. The arrangement also comprises an electronically reconfigurable switch matrix. The switch matrix comprises a plurality of segment lines (or other transmission media) each of which is used to form one collision domain or Ethernet segment. Switch elements under the control of a microcontroller selectively connect particular repeater groups (and the associated user groups) to particular segment lines to form Ethernet segments, each Ethernet segment being a single collision domain. Internetworking devices such as bridges and routers may also be connected to the switch matrix to interconnect particular collision domains.

Abstract: A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding.In particular, the invention relates to a quantization biased, activity based inter/intra decision.

Abstract: A process to determine the response pressure of a brake in a braking system of a vehicle comprises: measuring the existing vehicle deceleration of the vehicle to determine a value of ground-vehicle deceleration, supplying a test pressure to the brake, measuring the deceleration of the vehicle after the test pressure has been supplied to the brake to determine a value of vehicle test deceleration, and comparing the value of ground-vehicle deceleration and the value of vehicle test deceleration. If the value of vehicle test deceleration is greater than the value of ground-vehicle deceleration by more than a predetermined tolerance value, the steps of the process are repeated with a reduced test pressure until the difference between the values of ground-vehicle deceleration and vehicle test deceleration is no more than the predetermined tolerance value.

Abstract: A manufacturing process for a CMOS cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer between the buried contact and its adjacent interconnect polysilicon element. A self-aligning silicide process (salicide) is used to coat the interconnect polysilicon, the cavity, and the buried contact, to form a continuous electrical connection between the interconnect polysilicon and the buried contact.

Abstract: A converter interface device transforms an incompatible first central processing unit (CPU2) chip into a chip compatible with a CPU1 chip. The CPU1 compatible chip, containing the CPU2, is interchangeable with the CPU1 chip. The converter interface device allows CPU2 to appear to a computer system as having the same pins and pin configuration as the CPU 1. The converter interface device has an address converter, a data converter and a control bus converter. These converters convert CPU2 signals into signals which are CPU1 compatible. In addition, the converter interface device has a bus decoder which decodes the converted CPU1 compatible signal of CPU2 and outputs a signal to a CPU switch unit. The CPU switch unit receives an external CPU select signal, and outputs a CPU1 and CPU2 enable/disable signals. Therefore, a computer system can be upgraded from CPU1 to CPU2, without having to discard the motherboard and software associated with the older CPU1.

Abstract: A buried bit line ROM is disclosed having orthogonal sets of buried bit lines and polysilicon word lines. Polysilicon spacers are disposed on either side of each of the bit lines. The polysilicon spacers are slightly doped. The bit lines have a doping profile so that the edges of each bit line is doped less and the center of each bit line is doped more.

Abstract: A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped poly region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the poly region. An oxide region is provided on a portion of the first region surface adjacent to the poly region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a poly region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the poly region into the first region. The third region is then formed adjacent to the second region.

Abstract: A baby cry recognizer is disclosed which includes an amplifier circuit for amplifying a received sound signal. In response to the amplified sound signal, a pulse generator circuit generates a pulse signal having zero crossings which are aligned with zero crossings of the amplified sound signal. The pulse signal, in turn, is inputted to a signal recognition circuit. The signal recognition circuit is capable of obtaining the zero crossing rate of the pulse signal during each of a preselected number of frames in a predetermined length time interval. The signal recognition circuit then determines if the zero crossing rate of the pulse signal, in more than a first threshold number of this preselected number of frames, is within a particular frequency range. The signal recognition circuit also determines if the zero crossing rate of the pulse signal over the entire time interval is greater than or equal to a second low threshold but less than or equal to a third high threshold.