Abstract: A multiport memory in one embodiment of the invention includes a memory cell array, where each column in the array has two exterior complementary bitline pairs and zero, one, or more interior complementary bitline pairs. Across each pair of adjacent columns in the array, the adjacent exterior bitline pairs are associated with the same port in the multiport memory. In addition, within each column, the two exterior bitline pairs have the same, non-zero number of crossovers, and, across each pair of adjacent columns, the exterior bitline pairs have different numbers of crossovers. Furthermore, each column has at least one reference signal line located between the two exterior bitline pairs.