Abstract: In one embodiment, a node-implemented method for performing analysis of traffic within a packet communications network. First, the node measures a traffic aggregate at specified nodes within the network with regard to a packet set of interest. Each traffic aggregate (i) is a set of packets, observed at one of the specified nodes, having a common characteristic and (ii) is measured at one of the specified nodes by creating a digest for the packets having the common characteristic. The digest characterizes the traffic aggregate without containing the actual packets themselves. Next, the node formulates an intersection set cardinality determination for a network traffic-characterizing parameter to be measured in the network utilizing the digests characterizing the traffic aggregates. Next, the node solves the set cardinality determination for the network traffic-characterizing parameter to be measured.

Abstract: In one embodiment, a method for estimating the cardinality of one or more tags in a system that has the one or more tags and one or more readers. The reader issues a command requesting that the tags identify themselves. The command includes timing information defining a total number of timeslots. In response to the command, each of the one or more tags (i) selects a timeslot in which to reply to the command and (ii) issues a reply in the selected timeslot.

Abstract: The span of a linear transversal equalizer filter moves according to the current positions of the multi-paths to a receiver. The alignment of the filter span is measured quantitatively with respect to the current positions of the multi-paths. Adjustments are made to the filter span to enable the linear transversal filter to capture most of the available energy of the transmitted signal. The low-pass-filtered magnitudes of tap weights of the linear filter are multiplied with values of a function which has zeroes at desired points for the larger tap weights, and a gradient of the function at its zeroes being non-zero. The magnitude of the alignment measurement signal is used as a quantitative measure of the alignment of the equalizer span, while the sign of the alignment measurement signal can be used to decide the direction that the span should be moved in.

Abstract: In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.

Abstract: A buffer for a programmable logic device has programmable current sink and source circuitry and an independently programmable common-mode voltage reference source. An amplifier, responsive to a common-mode voltage detector and the voltage reference source, forces a common-mode voltage of an output signal from the buffer to approximate the voltage from the common-mode voltage reference source.

Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Abstract: An apparatus for error-correction encoding information includes, in one embodiment, an outer encode that generates algebraically decodable data, the outer encoder operatively coupled to one or more inner encoders that generate iteratively decodable data. The outer encoder is adapted to encode a group of (q?r) original data symbols using r code symbols to produce q outer-encoded symbols, wherein the coding gain of the outer encoder provides for the correction of up to x symbol errors and (r?2x) symbol erasures where r is an integer greater than zero and x is an integer such that 0 ? x < r 2 . The one or more iterative EC-inner encoders are adapted to inner encode each of the q outer-encoded symbols or combinations of several outer-encoded symbols independently of the others, wherein each symbol is encoded with h additional code bits.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.

Abstract: A switched-current oscillator having a dc current source adapted to charge a capacitor so that the capacitor charging time is controlled based on a sequence of (pseudo)randomly selected values, each of those values defining a corresponding charging time. A discharge device is adapted to discharge the capacitor if the voltage across the capacitor reaches a threshold voltage, at which point the next value in the sequence is selected to determine the next charging time. A square-wave clock signal having spread-spectrum characteristics is generated in the oscillator by using the series of charge-discharge cycles corresponding to the sequence of randomly selected values to toggle a flip-flop operating as a delay line and zero-order hold.

Abstract: The present invention enhances the dynamic frequency selection 9DFS) algorithms used in Wireless LANs by adding a channel swapping mechanism. The aim of the traditional DFS algorithm is to dynamically select channels in a wireless LAN in such a way that the best performance is achieved. However, not always the optimal channel selection is achieved. This invention describes an addition to the DFS algorithm in such a way that two APs can decide to swap channels instead of one AP switching to another channel. To avoid the problem of sub-optimal channel selection, a requesting AP sends Swap Requests to other APs in order to sense the willingness of other APs to swap channels with the requesting AP.

Abstract: An amplifier adapted to generate an analog output signal in response to a digital input signal and having an output stage powered by a power-supply circuit, which generates one or more power rails for the output stage such that at least one of these power rails tracks the output signal and substantially represents a biased and half-wave rectified version of that output signal.

Abstract: Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchronization signal for the macrocell's channels. Each channel has a counter that implements a state machine used to drive the multiplexing processing, where the state machine is reset to a specified state upon receipt of each synchronization pulse in the synchronization signal.

Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.

Abstract: When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.

Abstract: A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and the divider generates the feedback signal for the PLL from the selected signal. In another embodiment, the divider generates a divided signal from one of the phase-shifted output signals, and a phase mixer generates, from the divided signal, a plurality of phase-shifted divided signals and selects, based on the phase-circuit signal, one of the phase-shifted divided signals as the PLL's feedback signal.

Abstract: A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target clock signal and a reference clock signal. In various embodiments of the invention, this count registration is implemented by multiplying the target clock signal, discerning two or more phases of a signal, and/or organizing a count pipeline. In a representative embodiment, an FLD of the invention has a counter circuit and a control circuit. The counter circuit has (i) a frequency multiplier adapted to multiply the frequency of the target clock signal to generate a multiplied signal, (ii) two target counters adapted to register counts based on occurrences of two different phases of the accelerated signal to generate two auxiliary numbers, and (iii) a multiplexer adapted to select an appropriate one of the auxiliary numbers as the count value related to the frequency difference.

Abstract: Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.