Abstract: Techniques are disclosed for determining if the decomposition of layout design data is feasible, and for optimizing the segmentation of polygons in decomposable layout design data. Layout design data is analyzed to identify the edges of polygons that should be imaged by separate lithographic masks. In addition, proposed cut paths are generated to cut the polygons in the layout design data into a plurality of polygon segments. Once the separated edges and cut paths have been selected, a conflict graph is constructed that reflects these relationships. Next, a dual of the conflict graph is constructed. This dual graph will have a corresponding separation dual graph edge for each separated polygon edge pair in the layout design data. The dual graph also will have a corresponding cut path dual graph edge for each proposed cut path generated for the layout design data. After the dual graph has been constructed, it is analyzed to determine which of the proposed cut paths should be kept and which should be discarded.

Abstract: A method and apparatus for generating a source illuminator profile and a mask design, subsequently optimizing the source illuminator profile and mask design based upon a set of target intensity profiles. In various implementations, the Lagrange method of optimization is employed to optimize the radiation source, wherein an optimum intensity for each pixel of the source is determined. Subsequently, a continuous tone mask is generated based upon the diffraction orders of the optimized source. With various implementations, the target intensity profile is generated by deriving a set of band limited target frequencies corresponding to the optical lithographic system. Subsequently, homotopy methods may be employed to optimize the source illuminator profile and the continuous tone mask based upon the set of band limited target frequencies.

Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and OPC verification and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.