Patents Represented by Attorney Meyertons Hood Kivlin Kowert & Goetzel, P.C.
  • Patent number: 8316291
    Abstract: Embodiments of methods, apparatuses, systems and/or devices for packaging an electronic document and/or displaying the package are disclosed. In one embodiment, a first document including one or more digital media assets may be packaged. Packing the electronic document may comprise generating a second document comprising a rendering of at least a portion of the first document, extracting at least a portion of the digital media assets from the first document into one or more electronic files, and generating an electronic file comprising descriptive data for at least a portion of the extracted digital media assets.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: November 20, 2012
    Assignee: Adobe Systems Incorporated
    Inventors: Bernd Paradies, Nils Hausig
  • Patent number: 8316212
    Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: November 20, 2012
    Assignee: Apple Inc.
    Inventor: Joseph A. Petolino, Jr.
  • Patent number: 8311552
    Abstract: The present invention facilitates dynamic allocation of home IP addresses for a mobile node, when it is roaming away from a home network and supported by a foreign network. After the mobile node obtains a care-of address from the foreign network, a stateful or stateless configuration process is used to dynamically allocate a home IP address for the mobile node. In the stateful approach, a binding update message is used to request a home IP address for the mobile node from its home agent. In a stateless embodiment, the mobile node will create a home IP address, which is sent to the home agent for verification via the binding update message. The home agent will receive the home IP address in the binding update message, verify the home IP address, and send acknowledgement of the verification, assuming the home IP address is verified, to the mobile node.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: November 13, 2012
    Assignee: Apple Inc.
    Inventors: Mohamed Khalil, Haseeb Akhtar
  • Patent number: 8311129
    Abstract: In various embodiments, temporal filtering may be used to reduce noise over time in a series of video frames. A temporal filter may use previous filtered frames to reduce the noise in a current frame. For example, a temporal filter may filter noise in still parts of an image more strongly than in moving parts of the image. In some embodiments, a temporal filter requiring less processing power may include a method for detecting motion between a set of pixels and applying the temporal filter based on the detected motion. For example, if substantial motion is not detected, the temporal filter for the block of pixels may be stronger (i.e., reduce more noise) than the temporal filter applied to a block of pixels for which substantial motion has been detected.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: November 13, 2012
    Assignee: LifeSize Communications, Inc.
    Inventor: Michael V. Jenkins
  • Patent number: 8310268
    Abstract: This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: November 13, 2012
    Assignee: Apple Inc.
    Inventor: Mark H. Nodine
  • Patent number: 8312167
    Abstract: A method and apparatus for timely delivery of classes and objects is provided. A header comprising timing information is attached to said classes and/or objects. A “start loading” time and a “load by” time are specified in the header. Other classes and/or objects to be loaded are also specified in the header. Optional compression, security, and/or error resilience schemes are also specified in the header. A process for creating the header and attaching it to a class or object is provided. A process for receiving and processing a class or object with an attached header is provided. Embodiments of the invention allow timely delivery of classes and/or objects over a wide variety of transport mechanisms, including unreliable transport mechanisms and those lacking any guarantees of timely delivery.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: November 13, 2012
    Assignee: Oracle America, Inc.
    Inventors: Viswanathan Swaminathan, Gerard Fernando, Michael Speer
  • Patent number: 8311917
    Abstract: Methods and apparatus for managing collateral based transactions are disclosed. In one embodiment, one or more processors perform defining collateral for a financial transaction, assessing a valuation of the collateral based upon a difference between a material value and a legal tender value of the legal tender precious metal coins, and determining terms of the financial transaction based on the valuation. In some embodiments, the collateral includes one or more legal tender precious metal coins.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: November 13, 2012
    Assignee: Gold Innovations, LLC
    Inventor: Omar Besim Hakim
  • Patent number: 8312461
    Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO) configuration registers corresponding to hardware resources. A system processor may allocate the plurality of hardware resources to one or more functions, and to populate each entry of the resource discovery table for each function. The processing units may execute one or more processes. Given processing units may further execute OS instructions to allocate space for an I/O mapping of a PIO configuration space in a system memory, and to assign a function to a respective process. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: November 13, 2012
    Assignee: Oracle America, Inc.
    Inventor: John E. Watkins
  • Patent number: 8312298
    Abstract: A PXI Express controller may be configured to support at least three different conditions under which the controller may be turned on. If a chassis (e.g. a PXI Express chassis) interfacing with the controller has a power button, the first condition (which may be considered normal operation) may be met when the power button is being pressed at a time auxiliary power is present. When the chassis does not have a power button, the second condition may be met when the power is switched on at a time auxiliary power is present, and the third condition may be met when the power is switched on at a time auxiliary power is not present. A state-machine comprised in the PXI Express controller may be configured to interface with a chipset equally comprised in the PXI Express controller, to perform the control functions required to provide the support for the three different conditions.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: November 13, 2012
    Assignee: National Instruments Corporation
    Inventors: Keith D. Peterson, Jeffrey L. Kennedy
  • Patent number: 8311024
    Abstract: The present invention provides a control function in an access point, switch, or like node on a wireless local area network. The control function operates to ensure frames transmitted by a user terminal are transmitted using an appropriate transmission priority scheme. The control function will assist and provide an appropriate priority level to the user terminal. Frames transmitted from the user terminal are passed through the control function, which will analyze priority level information provided in the frames to determine if the frames were transmitted using the appropriate transmission priority scheme. An enforcement action may be taken in response to identifying frames that were not transmitted using the appropriate transmission priority scheme.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: November 13, 2012
    Assignee: Apple Inc.
    Inventors: Osama Aboul-Magd, Hesham Elbakoury, Sameh Rabie
  • Patent number: 8312525
    Abstract: A method for authenticating an entity at a first data resource, the method comprising the steps of: sending a first request token from the entity (100) to a token distribution unit (20) to request a first one-way authentication token, the first request token being a function of authentication information provided by the entity (100); sending the first one-way authentication token from the token distribution unit (20) to the entity (100); sending the first one-way authentication token from the entity (100) to the first data resource (200) to authenticate the entity (100) at the first data resource (200); sending the first one-way authentication token from the first data resource (200) to the token distribution unit (20) to validate the first one-way token; and invalidating the first one-way token.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: November 13, 2012
    Assignee: Software AG
    Inventors: Eckehard Hermann, Dieter Hermann Kessler
  • Patent number: 8311964
    Abstract: A system and method for efficiently reducing a number of duplicate blocks of stored data. A file server both removes duplicate data and prevents duplicate data from being stored in the shared storage. A sampling rate may be used to determine which fingerprints, or hash values, are stored in an index. The sampling rate may be modified in response to changes in characteristics of the system, such as a change in the shared storage size, a change in a utilization of the shared storage, a change in the size of the storage unit, and reaching a threshold corresponding to utilization of the index. Also, a small cache may be maintained for holding fingerprint and pointer pair values prefetched from the shared storage. Each prefetched pair may be associated with data corresponding to a previous hit in the index. The association may be related to spatial locality, temporal locality, or otherwise.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 13, 2012
    Assignee: Symantec Corporation
    Inventors: Petros Efstathopoulos, Fanglu Guo, Dharmesh Shah
  • Patent number: 8309457
    Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: November 13, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
  • Patent number: 8310291
    Abstract: A delay locked loop (DLL) having an accelerated training interval during a voltage change. An integrated circuit (IC) includes a master DLL configured to generate a clock signal based upon a reference clock signal. The master DLL may train to the reference clock signal in response to a control signal. The IC also includes a control unit that is coupled to the master DLL and may provide the control signal at a first interval in response to receiving an indication that a supply voltage is being changed, and provide the control signal at a second interval in the absence of the indication.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: November 13, 2012
    Assignee: Apple Inc.
    Inventors: Erik P. Machnicki, James D. Ramsay, Sanjay Mansingh
  • Patent number: 8312187
    Abstract: An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: November 13, 2012
    Assignee: Oracle America, Inc.
    Inventors: Elisa Rodrigues, John E. Watkins
  • Patent number: 8307235
    Abstract: A system may include a plurality of subsystems, e.g. instrumentation units housed in separate chassis, each chassis including multiple instrumentation devices, e.g. data acquisition cards. Each subsystem may generate a local reference clock, which may be phase aligned and locked with respect to one or more similar reference clocks of other subsystems, via a high-level precision time protocol (PTP). Each instrumentation device within a given subsystem may generate its own sample clock based on the local reference clock, and may generate its own trigger clock based on its own sample clock. All trigger clocks may be synchronized with respect to each other through a future time event issued using the PTP, and each instrumentation device may then use its trigger clock to synchronize any received trigger pulses, which may also be issued through future time events using the PTP.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 6, 2012
    Assignee: National Instruments Corporation
    Inventors: Kunal H. Patel, Adam C. Ullrich, Kalyanramu Vemishetty, Stephen A. Hanssen
  • Patent number: 8307346
    Abstract: Transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, while in fact they do not. Techniques that employ transactional memory may allow a debug user to define a group of variables as an atomic group and may ensure coherent or consistent access to variables of the atomic group. These techniques may facilitate the debugging of programs that are executed using transactional memory. Unlike conventional debuggers, debuggers that employ these techniques may be adapted to provide a coherent or consistent view of variables in a system that employs transactional memory. The atomic group may be accessed for viewing and/or modifying during debugging using a transaction, regardless of whether all or less than all of the variables in the atomic group are modified.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: November 6, 2012
    Assignee: Oracle America, Inc.
    Inventors: Yosef Lev, Moir S. Mark
  • Patent number: 8305125
    Abstract: A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: November 6, 2012
    Assignee: Apple Inc.
    Inventors: Bo Tang, Edgardo F. Klass
  • Patent number: 8307347
    Abstract: System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: November 6, 2012
    Assignee: National Instruments Corporation
    Inventors: Paul F. Austin, Ramprasad Kudukoli
  • Patent number: 8307289
    Abstract: System and method for configuring a client system, e.g., a measurement system. First input is received from a client system over a network requesting access to a plurality of configuration diagrams comprising respective solutions to respective tasks. At least a subset of the plurality of configuration diagrams is displayed on a display device of the client system for viewing by a user. Second input is received from the client system selecting one of the displayed configuration diagrams indicating a solution for a task to be performed by the client system. The solution is provided to the client system over the network, and may include the selected configuration diagram and/or pricing information for proposed products. The configuration diagrams are stored in a configuration diagram database. The stored configuration diagrams may be pre-defined solutions for pre-defined tasks, generated in response to received user requirements, and/or received from client systems and/or vendors.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: November 6, 2012
    Assignee: National Instruments Corporation
    Inventors: Mohammed Kamran Shah, David W Fuller, III, Jeffrey N. Correll, Brian H. Sierer