Abstract: In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock cycle before data. The pre-computed memory management unit policy is registered and used for controlling a pipeline stall to ensure that a non-bufferable write is pipeline-protected, so that no non-bufferable location is bypassed from within the pipeline, and so that a subsequent non-bufferable read will get data from a final destination. A read request is bypassed only after a corresponding write request is updated in a write pending buffer. The write request is decoded with the write request aligned to data. The write request is registered in the write pending buffer. Arbitration logic is allowed to force the pipeline stall for a region that will have a write conflict. Read requests are stalled to protect against write hazards.

Abstract: In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units.

Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.

Abstract: A digital signal processor (DSP) includes an instruction buffer queue (IBQ) with multiple lines, as well as a modifiable fetch advance parameter to specify a fetch advance setting for the IBQ. The DSP also has a control flow module. In response to execution of a program in the DSP, the control flow module may automatically determine whether a branch has been predicted for the program, or for a portion of the program. The control flow module may automatically reduce the fetch advance parameter in response to determining that a branch has been predicted for the program. Also, the control flow module may automatically increase the fetch advance setting in response to determining that no branch has been predicted for a portion of the program. Other embodiments are described and claimed.

Abstract: In a computing system, a computer-readable medium is for storing information. At least one computing device is for receiving at least one installation file and multiple installable files. The installation file includes at least one table for specifying an installation of a subset of the installable files. Also, the computing device is for identifying the subset in response to the table. Moreover, the computing device is for outputting the installation file and the identified subset of the installable files for storage by the computer-readable medium, such that less than all of the installable files are concurrently stored by the computer-readable medium.

Abstract: A computer system includes circuitry for selecting among first and second parameters in response to a command. The parameters are for use in computing a password. The circuitry is for reading content of the selected parameter from a computer-readable medium and computing the password in response thereto. The password computed in response to content of the first parameter is different from the password computed in response to content of the second parameter. Also, the circuitry is for concealing the password from a user of the computer system.

Abstract: A computing device receives first information about a customer. The computing device outputs second information to at least first and second loan sources. The second information includes at least a portion of the first information. From the first and second loan sources, the computing device receives submissions of respective first and second bids for providing a loan to the customer for purchase of an item. The computing device identifies at least one of the first and second bids as being most favorable. To the customer, the computing device outputs third information about the identified bid, including an identity of at least one of the loan sources that submitted the identified bid.

Abstract: A system includes a computing device for storing criteria under which a customer is authorized to purchase a physical item. The computing device receives a request from the customer. In response to the request satisfying the stored criteria, the computing device outputs a signal for purchasing the physical item. The stored criteria may include a monetary budget for purchasing the physical item. The computing device is for modifying the stored criteria to reduce the monetary budget in response to the signal.

Abstract: According to a first model of an operation of circuitry, a first set of estimates of the operation is generated in response to a set of conditions, including a first estimate of the operation in response to a first condition. According to a second model of the operation, a second set of estimates of the operation is generated in response to the first condition and the first set. In response to a comparison between the first estimate and the second set, a subset of the first set is selected. According to the second model, an estimate of the operation is generated in response to a second condition and the selected subset.

Abstract: A processing system and method of operation are provided. A particular instruction is dispatched to execution circuitry for execution. After dispatching the particular instruction, an execution serialized instruction is dispatched to the execution circuitry prior to finishing execution of the particular instruction.

Abstract: A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.

Abstract: From a first circuit, information is output in response to acknowledgement signals. From a second circuit, the acknowledgement signals are output in response to the second circuit receiving portions of the information from the first circuit. The portions and the acknowledgement signals are output asynchronously with respect to one another. With at least one of the first and second circuits, a signal having a logic state is received, the logic state is latched, and an operation is performed in response to the latched logic state.

Abstract: First current is conducted through a first path to adjust a voltage at a node toward a predetermined level in response to the voltage being within a first subrange of voltages. Second current is conducted through a second path to adjust the voltage at the node toward the predetermined level in response to the voltage being within a second subrange of voltages.

Abstract: In a method and system for storing information within a set of a cache memory, the set has multiple locations. The information is stored at a selected one of the locations. The selected location satisfies one of the following conditions (a), (b) and (c): (a) the selected location is invalid; (b) each of the locations is valid, and the selected location is unmodified; (c) each of the locations is valid and modified, and the selected location is least recently used among the locations.

Abstract: A method and system for reducing bus traffic in a multiple processor system having a shared memory and processor related private caches. Store multiple word instructions are evaluated to determine whether a full cache line is to be modified. If the full cache line is to be stored, a cache line kill is issued on the system bus and the cache line is written to the cache. Any store operation of single word, or multiple words extending over portions of a cache line, invokes conventional memory coherence processes.

Abstract: While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0<M<N.

Abstract: From a first circuit, first information is output in response to acknowledgement signals. From a second circuit, second information and the acknowledgement signals are output. The second information and the acknowledgement signals are output in response to the second circuit receiving portions of the first information from the first circuit during a functional mode of operation. The portions and the acknowledgement signals are output asynchronously with respect to one another. From a third circuit, third information is output in response to the second information. From a test circuit, the second information output from the second circuit is specified, so that the third circuit outputs the third information in response to the specified second information independent of the first information output from the first circuit during a test mode of operation.

Abstract: A first group of memory locations stores information. The first group is arranged into multiple congruence classes of memory locations. The congruence classes include a first congruence class having more than one memory location. A second group of memory locations stores information from the first group of memory locations. Directory locations store information relating the first and second groups of memory locations. The directory locations include a first directory location able to store information relating a particular one of the second group of memory locations to any memory location of more than one of the congruence classes including the first congruence class.

Abstract: A method and system are provided. A clock signal is input and output at first and second nodes of integrated circuitry. The first node is connected through a selected one of a plurality of metallization paths of the integrated circuitry to the second node. Each of the metallization paths is connectable between the first and second nodes for delaying the clock signal by a respective amount of time between the first and second nodes, so that the clock signal at the second node is always delayed relative to the first node by the respective amount of time of the selected metallization path.

Abstract: While dispatch circuitry operates in a first power mode, per cycle of the dispatch circuitry, up to N number of instructions are dispatched to execution circuitry for execution, where N is an integer number and N>1. While the dispatch circuitry operates in a second power mode, per cycle of the dispatch circuitry, up to M number of instructions are dispatched to the execution circuitry for execution, where M is an integer number and 0<M<N.