Abstract: According to an aspect of the present invention, a power detector including a photodiode and a logarithmic transimpedance amplifier is mounted inside a hermetically sealed package in such a way that the photodiode and the logarithmic transimpedance amplifier are located on the same thermally conductive substrate.

Abstract: Described are a system and method for monitoring and characterizing a stimulus in order to detect transient phenomena. An analog signal represents the stimulus. Conversion circuitry receives the analog signal and continuously converts the analog signal into digital data. Digital circuitry continuously receives the digital data from the conversion circuitry and dynamically computes from the digital data a value that characterizes a parameter of the stimulus while the digital circuitry continuously receives new digital data from the conversion circuitry. The digital circuitry can be reconfigured to characterize a different parameter for the same type or for a different type of stimulus.

Abstract: A very thin portable computer includes a computer housing for holding electronic components and a battery housing movably mounted external to the computer housing, the battery housing adapted for holding batteries for supplying power to the electronic components. The battery housing is rotatably mounted on the computer housing such that the battery housing rotates between a closed position wherein the battery housing covers the rear side of the computer and an open position wherein the battery housing exposes connectors on the computer housing and elevates the rear side of the computer housing to an angle convenient for typing.

Abstract: A method and related apparatus enables one station on a local area network (LAN) 24 to remotely and securely modify sensitive information of another station on the LAN 24. A workstation 12, acting as a remote management console, generates a wake-up packet 32 or 42 intended for a desktop computer 14 on the LAN 24. A network interface 64 receives and processes the wake-up packet, and issues a signal to wake up the desktop computer. In response to the signal, the desktop computer 14 bootstraps. Data indicating that the network interface 64 has issued the signal is stored in register 104. In the course of bootstrapping, the processor 78 examines the register 104 to determine that the network interface 64 has initiated the wake-up of the desktop computer 14. Once this determination is made, the write protection circuitry 76 places the BIOS ROM 74 in an unprotected state wherein the contents BIOS ROM 74 can be modified by the workstation 12.

Abstract: A data block in a RAID array is reconstructed under the control of metadata recorded on the RAID array. The RAID array has a plurality of members, each member being a data storage device. The metadata includes device metadata for data blocks recorded on each member and RAIDset metadata for RAID protected data blocks recorded across the members of the RAID array. The RAID protected data blocks include user data blocks, RAIDset metadata blocks and parity data blocks. The data blocks are reconstructed by detecting from a device FE bit in the device metadata that a bad data block corresponding to or associated with the device FE bit needs to be reconstructed. The data is read from each data block, other than the bad data block, in the same RAID sliver with bad data block. A RAID sliver of data blocks includes all the data blocks in a RAID protected sliver of data blocks.

Abstract: A graphical figure is defined. A library of simple tasks is created using trial stimulus/response combinations. A hill climbing algorithm is employed to find a stimulus/response combination that accomplishes an optimum result for each task. An animation editor facilitates the creation of composite animated sequences by causing the retrieving and displaying of a first simple task, controlling the length of time the first simple task is displayed and by causing the retrieving and displaying of additional simple tasks and controlling the length of time the additional simple tasks are displayed.

Abstract: A printer architecture utilizing network resources to distribute printer controller and translator functions and thereby process several print jobs in parallel. The several print jobs can be transferred, in order of completion, to a print engine for a high speed real time printing operation, or stored as pre-rasterized images for subsequent access and delivery to the print engine.

Abstract: An apparatus is provided to reduce the amount of EMI generated by a circuit. The grounding of an enclosure is improved by providing a number of shaped protuberances, the protuberances having an end that penetrates a conductive region of a circuit board, such that when the circuit board is mounted to the support member, the protuberances make a penetrating electrical contact and provides for additional ground paths, thereby reducing the EMI generated by the assembly.

Abstract: During operation of a computer system, index records and data records of a data structure are organized in a hierarchical manner, with index records being at a higher level of the hierarchy than the data records referenced by the index records. While the data structure is manipulated, the data records are stored in a random access memory. Modifications made to the data structure are chronologically written to a disk storage in a bottom-first/top-last order of the hierarchy for persistent storage as a database. A back-up copy of the database is made by storing the data and index records of the database in a top-first/bottom-last order on a sequentially readable media. A temporal and spatial view of a portion of the database can be obtained by accessing the index records and the data records of the database or the back-up media in the top-first/bottom last order.

Abstract: In a computer network, a method of random sampling of network packets is provided including the steps of providing a network switch, providing a monitoring device, the monitoring having a memory and a data storage unit, providing a network interface to connect the network switch to the monitoring switch, selecting a reference error check code value in the monitoring device, receiving a first network packet from the network switch, comparing, in the network monitoring device, the reference error check code with an error check code of a first network packet, storing the first network packet in the monitoring device if the error check code value of the first network packet matches the reference error check code of the first network packet, and repeating the steps of receiving, comparing and storing for subsequent network packets.

Abstract: Disclosed are multilayer electrical structures comprising a discrete, partially-cured, microsphere-filled resin layer, and a method for fabricating such multilayer electrical structures using a carrier member to support and introduce the microsphere-filled resin layer.

Abstract: The invention relates to an enclosure for computers that is formed by slidably joining together two chassis portions. A groove formed in a wall of one chassis portion mates with a tongue formed in a wall of the other chassis portion. The tongue enters one end of the groove and slides throughout the groove's length until the two chassis portions become fully joined and form a completed enclosure. The combination of the tongue and groove forms a slidable tongue and groove joint. When both chassis portions are made of electrically conductive material, the tongue and groove joint effectively inhibits the passage of electromagnetic radiation through the seam that forms at the juncture of the two chassis portions.

Abstract: An apparatus and method of implementing an enhanced PCI interrupt controller which accommodates the industry standard wire-or functionality. With such an arrangement a method and apparatus to identify a source of a PCI interrupt without the need for polling is implemented with a register-based architecture and staged initiator decode. The invention implements both the default industry standard and a non-polled (interrupt accelerator) mode.

Abstract: An architecture, module set and platform to provide total power protection from utility disturbances. Power supplies employing the invention are built on power buses for utility AC input, battery DC input and conditioned AC output housed in the platform and employ modular line-to-AC-or-DC power-factor-correcting converters and battery/charger sets either housed in the platform or integrated as part of the front end power supply for a critical load such as a computer.

Abstract: A system and method and computer program product for encrypting data communications comprising the generation of a salt at a data transmitting system and combination of the salt with a primary encryption key known at the data transmitting system and a data receiving system. The salt and the primary encryption key are hashed to produce a transmitting encryption key and a data message is encrypted with an encryption function utilizing the transmitting encryption key to produce a ciphertext message. The salt and the ciphertext message are transmitted to the data receiving system where the salt and the primary encryption key are hashed to produce a receiving decryption key and the data message is retrieved by performing a symmetrical decryption function on the ciphertext message and the receiving decryption key.

Abstract: Arbitration means for arbitrating between computer devices A to F which compete for access to a common bus. The system provides cascaded round-robin units. Unit RR1 has ports A, B, C, and X in sequence, with port X coupled to round-robin unit RR2, which has ports D, E, F in sequence. On each cycling of unit RR1 past C to A, unit RR2 is checked and the next one of devices D to F (in the sequence determined by unit RR2) has the opportunity of bus access. A gating circuit 13 can further restrict bus accessing by unit RR2's devices, by timing or counter control. A third round-robin unit can be added coupled to unit RR1 (which would have ports A, B, C, X,Y) or to unit RR2 (which would have ports D, E, F, Y). The assignment of devices to ports can be controllable by a matrix switch and device assignment memory.

Abstract: A pattern match method is the primary component of any rule-based inference engine or database search method. Equivalence class projection is used in a discrimination match network, such that only equivalence class tokens (and not working memory objects) are propagated down the network, then only the first object which is a member of any specific equivalence class will cause an actual propagation down through the net. Subsequent changes which are either the creation of new objects which are members of a known equivalence class or the removal of any object but the last member of that equivalence class can totally avoid propagation downward in that section of the discrimination network.

Abstract: An architecture, module set and platform to provide total power protection from utility disturbances. Power supplies employing the invention are built on power buses for utility AC input, battery DC input and conditioned AC output housed in the platform and employ modular line-to-AC-or-DC power-factor-correcting converters and battery/charger sets either housed in the platform or integrated as part of the front end power supply for a critical load such as a computer.

Abstract: A selective multilevel caching method and system including a main memory and a plurality of cache memories are disclosed. The main memory and cache memories are arranged in a multilevel hierarchy: the main memory is at the lowest hierarchical level; the cache memory that is coupled directly to the central processing unit (CPU) is at the highest hierarchical level; and the remaining cache memories are coupled in the hierarchy at intermediate hierarchical levels therebetween. Each hierarchical level contains cache logic as well as a cache memory. Each cache logic responds to a cache level code that is associated with an address specified in each CPU read or write data request. The cache level code specifies the highest hierarchical level at which data associated with the data request may be written. Each cache logic uses the cache level code to determine if data will be written to the cache memory at the same hierarchical level as that cache logic. Each CPU write request further includes a cache control code.

Abstract: A read buffering system and method employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.