Abstract: Emulation of a hardware peripheral is accomplished through use of object oriented software and runs in an object oriented environment. Particular adaptation of an emulation to enable specific data storage magnetic tape drive peripheral is described. Use of emulators in general enables continued reliance on legacy hardware and software without maintaining an entire suite of legacy hardware. Simplified emulation structure enabled by object oriented programming described herein makes migration from legacy systems feasible in stages at relatively low cost. In set-up and in use, users can have control over instances of emulator objects, including association with data files that operate as virtual storage media whether initially associated with the emulator or not, using a simple window-based interface for choosing particular data files, opening them, opening new instances of emulator objects and so forth. Variations are also described.

Abstract: In particular, a system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a collection of coordinated collector system to collect trace data for a plurality of processor busses operating at the same time in a multiprocessor computer system under test. Pipelined bus communications on the processor bus are aligned, in one mode, and in another, multiple instructions on split domain busses are aligned. In both cases a time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data. All time stamps from the various busses being studied and from which trace data is being collected have the same values at any given time so that the data collected from each bus can be coordinated with data from the other busses of the plurality by the reading of the time stamps.

Abstract: Communications between an adapter card and a host computer system are established by embedding a server program within a BIOS extension stored in a memory on the adapter card. The BIOS extension is loaded into the host memory during normal execution of the host system BIOS for execution by the host processor. When executed by the host processor, the BIOS extension code copies the server program embedded within it to a new location in host memory, and then hooks the new location of the server program to a pre-selected interrupt of the host computer system to cause the host processor to initiate execution of the server program on the host computer system upon a subsequent occurrence of that interrupt. When executed on the host computer, the server program then establishes two-way communications with a client program executing on the adapter card.

Abstract: Apparatus and methods for translating test vectors between a format suitable for use with a standalone integrated circuit tester and a format suitable for use with an in-circuit tester are disclosed. Methods according to the invention include: providing a first test file in a first format that is suitable for use with the standalone integrated circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester. Methods according to the invention also include: providing a first test file in a first format that is suitable for use with the in-circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the standalone integrated circuit tester. Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.

Abstract: Customer record systems for multinational companies advantageously store both Latin character set (language of the database user) and customer-local language forms of the information so that mailings to customers can be accomplished with printing in the local language. Further, web access by customers into their information can also be displayed in local language format from this system. Limiting the local language storage to that information that is needed to communicate to the customer in customer's location provides full access to all transactional information to the owner or user of the database. Translating all customer information into Unicode provides a single uniform database into which these mixed language records can be stored. Variations in signaling to the translation mechanism are provided so that use of local language terminals can be used.

Abstract: A processor bus bridge includes a buffer space disposed between a first bus and a second bus. The first bus is operated in a first mode by a first processor and the second bus is operated in a second mode by a second processor. The first bus has an electrical structure which is different from the electrical structure of the second bus. The first mode may also differ from the second mode. The processor bus bridge has a protocol logic module disposed between the first processor and the second processor for controlling data transfer across the buffer space in the first and second modes. Thus, the bus bridge enables communications between dissimilar processor buses while increasing performance and reducing CPU overhead.

Abstract: Methods and apparatus that enable a transport protocol executing on a first computer system to be utilized by applications executing on a second computer system which is directly interconnected and closely coupled to the first computer system. An interconnection couples an input/output (I/O) subsystem of the first computer system to an I/O subsystem of the second computer system and provides a path over which data can be transmitted between the first and second computer systems independent of a network interface card, and an interconnection messaging system executing on the first and second computer systems provides general purpose transport interfaces between said first and second computer systems.

Abstract: A method and a data file structure (100) for embedding a digital signature verification key (108) within a particular type of image data file enables validation of the image data (102a,b) autonomously—i.e. without consulting large external data bases of public keys or certificates.

Abstract: A computer-based administration tool migrates user's names and greetings from a first voice mail system to a second voice mail system. Illustratively, the administration tool accesses the first voice mail system for recording, or storing, each of a plurality of users names and greetings. The administration tool then sends them to the second voice mail system for use therein.

Abstract: A printed circuit board (PCB) comprises a number of electrically conductive layers. Instead of coating, or plating, a PCB through-hole with an electrically conductive material to form a via (for the purpose of connecting together signal paths across the electrically conductive layers)—the via is formed by placing a conductive stake, or conductive pin, in the through-hole.

Abstract: A system and method for coordinating a telephony session on a voice messaging platform with an e-mail session on an e-mail messaging platform in an integrated universal messaging system are disclosed. The method, which is carried out by the system, comprises the steps of: (a) receiving a call on the voice messaging platform placed by a subscriber from a telephone handset and processing the call on the voice messaging platform in accordance with a first call flow; (b) invoking from the first call flow, a second call flow that initiates access to the subscriber's account on the e-mail messaging platform, the second call flow executing in parallel with, and asynchronously of, the first call flow; (c) continuing to execute the first call flow while the second call flow is executing; and (d) playing one or more prompts by the first call flow, as needed, to mask at least a portion of any delays experienced in receiving a response from the second call flow.

Abstract: A system for providing, via a network, emulation of a console of a first computer system on a second, remotely located computer system on the network comprises an adapter card installed in the first computer system and a client program executing on the remotely located computer system. The adapter card comprises a local bus that interfaces to an input/output bus of the first computer system when the adapter card is connected to the first computer system, a graphics controller coupled to the local bus that interacts with the first computer system to generate a representation of a console screen of the first computer system, a network interface controller coupled to the local bus that provides a connection to the network, and a processor coupled to the local bus that determines changes in the representation of the console screen of the first computer system and that transmits information about the changes to the remotely located computer system via the network interface controller.

Abstract: A system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a small FIFO memory and skips unused bus cycles to avoid the requirement for memory speed to match the processor bus speed. Pipelined bus communications on the processor bus are aligned, in one mode, and in another, multiple instructions on split domain busses are aligned. In both cases a time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data.

Abstract: A test application allows configuration of test parameters and launches a voice processing engine and a timing object. The voice processing engine outputs data to the timing object. The timing object receives data, regularly removes data, and tracks the amount of data remaining in the timing object. The timing object reports an underflow if there is no data in the timing object and the voice processing engine has not signaled end of processing.

Abstract: A computer aided design (CAD) tool takes into account system-level design parameters by considering data from a number of printed circuit board (PCB)-related data files. In one embodiment, the CAD tool takes into account signal path length at the system-level for a computer system comprising more than one PCB. In another embodiment, the CAD tool provides a three-dimensional display for showing how at least one signal path traverses the computer system in going from one PCB to another PCB.

Abstract: A system of determining oscillation frequency of a ring oscillator formed on a chip. The system includes a ring oscillator formed on the chip for providing a ring clock signal having first periodic pulses, and a ring counter formed on the chip for providing a ring clock count value in response to the first periodic pulses. The system also includes a terminal for receiving a system clock signal having second periodic pulses, and a system counter formed on the chip for providing a system clock count value in response to the second periodic pulses. The oscillation frequency of the ring oscillator is determined based on the ring clock count value and the system clock count value.

Abstract: A data compressor includes a plurality of tandem coupled stages, each stage comprising a matrix of AND-gates and a matrix switch. An AND-gate has inputs responsive, respectively, to a representation of a prefix code and a representation of a character for energizing the AND-gate output. The AND-gate outputs are coupled, respectively, to the inputs of the matrix switch and the matrix switch outputs have respective string codes assigned thereto. The matrix switch is controllable for coupling any one of the matrix switch inputs to a selected one of the matrix switch outputs. Energization of an AND-gate output coupled to a matrix switch output provides a representation of the code assigned thereto. The provided representations of codes assigned to the AND-gates of a stage are coupled to the prefix code inputs of the AND-gates of the next following stage.

Abstract: The data compressor utilizes a plurality of subdictionaries arranged in levels for storing strings of data characters. The subdictionary at the first level stores two character strings and a subdictionary at a subsequent level stores strings that are one character longer than the strings stored in the subdictionary at the level prior thereto. A plurality of data characters are fetched from the input into an input buffer and applied to the respective levels. The subdictionary at a level is searched for the string comprising the string matched at the prior level extended by the fetched character applied to the level. The string code of a string matched at a level is cascaded to the next level. The longest match with the fetched characters is determined by one of the fetched characters resulting in a mismatch at one of the levels. The string code associated with the longest match is output.

Abstract: A data decompressor for decompressing an input stream of compressed codes to recover an output stream of data characters corresponding thereto. A plurality of character tables corresponding to respective characters store strings of data characters, the stored strings having respective string codes associated therewith. A string comprises a prefix string of at least one character followed by an extension character. A string is stored in the character tables by storing the code associated with the string prefix in the character table corresponding to the string extension character at a character table location corresponding to the string code of the string. The character tables are accessed with a currently received compressed code so as to recover a string corresponding thereto and the characters of the recovered string are output.

Abstract: An enhanced cache line directory entry includes at least one affinity bit that indicates an affinity for a particular type of cache line ownership. The affinity bit is used to modify a request for a cache line in accordance with the indicated affinity. The affinity bit may represent an affinity for read-only requests, and the affinity bit may represent an affinity for read-write requests. For example, if an I/O affinity bit is in the set state and an I/O device requests a cache line with read-write permission, the request may be converted to a read-only request in accordance with the indicated affinity. As another example, if a processor affinity bit is in the set state and a processor requests a cache line with read-only permission, the request may be converted to a read-write request. Software control of the affinity bits enables system performance to be tuned and cache coherency operations can thereby be reduced.