Abstract: A circuit for providing a plurality of output functions at respective outputs by detecting the presence of an unusual voltage applied at its input thereof, comprising input circuit coupled to the input for transferring the input signal to a first output when the input signal is within a predetermined voltage range. A detection circuit coupled to the input for providing a detection signal at an output thereof when the input signal level exceeds a predetermined level in a predetermined sense. A buffer stage coupled between the output of the detection circuit and a second output, responsive to the detection signal, for providing a first binary logic state of the second output.

Abstract: An analog-to-digital converter is provided wherein an analog input signal and one of a series of predetermined reference potentials are stored across first and second capacitors, respectively, to establish a balanced zero differential signal across the first and second inputs of a comparator. The output signal of the comparator drives a logic circuit for generating first and second portions of a digital control signal wherein the first portion selects between the lower resolution reference potentials searching for a first reference potential of the greatest value which when compared to voltage stored across the first capacitor provides the least magnitude differential signal across the first and second inputs of the comparator thereby resolving a major portion of the analog input signal.

Abstract: A current mirror provides an output current that is scaled in magnitude with respect to an applied input current includes first and second current turnaround circuits and circuitry coupled between the two current turnaround circuits which is responsive to the first current turnaround circuit for sourcing a current to the second current turnaround circuit the magnitude of which is scaled with respect to the input current that is sourced to the first current turn around circuit.

Abstract: An integrated circuit is disclosed having an output coupled to a capacitive load for sourcing or sinking current at said output to charge or discharge the load accordingly to a fixed voltage established by the circuit. The circuit includes an NPN transistor push-pull output stage and first and second current mirrors coupled to the push-pull output stage for establishing feedback in order to set a small quiescent current flow in the output stage. A NPN transistor having its collector-emitter conduction path coupled to the collector of the upper one of the NPN transistors provides the dynamic current thereto when turned on to provide the sourcing current flow through the latter.