Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator can include: (i) a filter network coupled to an output terminal, where an output voltage is generated at the output terminal from an input source; (ii) an active switch to connect the input source to the filter network by periodically operating between on and off states over a switching period, where a duty cycle of the on state relative to the switching period is modulated based on a PWM control signal; (iii) a comparator receiving an output feedback signal, a hysteresis signal, and a reference level, and providing the PWM control signal therefrom; and (iv) a hysteresis programming circuit generating the hysteresis signal, and a ramp control signal, where the hysteresis signal is programmed based on conditions at the input source and the output voltage to achieve a pseudo constant frequency operation.

Abstract: Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.

Abstract: Power converter circuits, structures, and methods are disclosed herein. In one embodiment, a hybrid converter can include: (i) a first switching device controllable by a control signal; (ii) an inductor coupled to the first switching device and an output; and (iii) a control circuit configured to receive feedback from the output for generation of the control signal to control the first switching device, where the control circuit includes a first detection circuit configured to detect first and second output conditions, the control circuit being configured to operate the first switching device in a switch control in response to the control signal when the first output condition is detected, and to operate the first switching device in a linear control region when the second output condition is detected.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a switching regulator can include: (i) a filter network coupled to an output terminal, where an output voltage is generated at the output terminal from an input source; (ii) an active switch to connect the input source to the filter network by periodically operating between on and off states over a switching period, where a duty cycle of the on state relative to the switching period is modulated based on a PWM control signal; (iii) a comparator receiving an output feedback signal, a hysteresis signal, and a reference level, and providing the PWM control signal therefrom; and (iv) a hysteresis programming circuit generating the hysteresis signal, and a ramp control signal, where the hysteresis signal is programmed based on conditions at the input source and the output voltage to achieve a pseudo constant frequency operation.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. In one embodiment, a power supply can include: (i) an input capacitor coupled to an input terminal that is coupled to a power source, where the power source provides power that is constrained by a predetermined limit; (ii) an output capacitor coupled to an output terminal that is coupled to a load, where the load has a first load condition or a second load condition; (iii) a first regulator to convert an input voltage at the input terminal to an output voltage at the output terminal to power the load; (iv) a second regulator coupled to the first regulator; and (v) an energy storage element coupled to the second regulator, where the second regulator delivers energy from the energy storage element to the first regulator to maintain regulation of an output voltage at the output terminal when in the second load condition.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; after the doped body region formation, forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; after the doped body region formation, forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.

Abstract: Power converter circuits, structures, and methods are disclosed herein. In one embodiment, a hybrid converter can include: (i) a first switching device controllable by a control signal; (ii) an inductor coupled to the first switching device and an output; and (iii) a control circuit configured to receive feedback from the output for generation of the control signal to control the first switching device, where the control circuit includes a first detection circuit configured to detect first and second output conditions, the control circuit being configured to operate the first switching device in a switch control in response to the control signal when the first output condition is detected, and to operate the first switching device in a linear control region when the second output condition is detected.

Abstract: A wire-free chip module and method. The wire-free chip module including a conductive pattern formed from at least a portion of a lead frame, the conductive pattern including a plurality of pads; at least two electrical components that includes an integrated circuit and a passive component, the integrated circuit and the passive component bonded to the plurality of pads by solder; and wherein the conductive pattern is disposed to interconnect at least a portion of the integrated circuit with the passive component.

Abstract: Methods, circuits, processes, devices, and/or arrangements for a non-volatile memory (NVM) cell operable at relatively low voltages are disclosed. In one embodiment, an NVM cell can include: (i) a gate over a charge trapping layer, the charge trapping layer being insulated from the gate by a first insulating layer, the charge trapping layer being insulated from a channel by a second insulating layer; and (ii) source and drain on either side of the channel, the channel being under the second insulating layer, where the NVM cell is configured to be erased by channel-induced hot holes (CHH).

Abstract: Methods, circuits, processes, devices, and/or arrangements for providing a non-volatile memory (NVM) cell are disclosed. In one embodiment, an NVM cell can include: (i) a floating gate in a gate layer, where the floating gate is over an insulating layer, and the insulating layer is over a first channel between first and second diffusion regions; and (ii) a control gate in the gate layer, where the control gate is configured to control the floating gate using direct sidewall capacitive coupling, and where a first coupling ratio from the direct sidewall capacitive coupling is greater than a second coupling ratio from the second diffusion region.

Abstract: Methods, circuits, devices, and/or arrangements for providing a non-volatile latch are disclosed. In one embodiment, a non-volatile latch can include: (i) a first non-volatile memory (NVM) cell coupled to a first supply, a first gate (e.g., a control gate), and an output node, where the first NVM cell is configured to be in a first state; and (ii) a second NVM cell coupled to a second supply, a second gate (e.g., another control gate), and the output node, where the second NVM cell is configured to be in a second state.