Patents Represented by Attorney Michael D. Plimier
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Patent number: 7772706Abstract: A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.Type: GrantFiled: December 27, 2007Date of Patent: August 10, 2010Assignee: Intel CorporationInventors: Sridhar Balakrishnan, Boyan Boyanov
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Patent number: 7723008Abstract: A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.Type: GrantFiled: March 22, 2005Date of Patent: May 25, 2010Assignee: Intel CorporationInventors: Robert P. Meagley, Heidi B. Cao, Kevin P. O'Brien
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Patent number: 7718528Abstract: A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.Type: GrantFiled: January 5, 2007Date of Patent: May 18, 2010Assignee: Intel CorporationInventors: Robert P. Meagley, Heidi B. Cao, Kevin P. O'Brien
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Patent number: 7217595Abstract: The invention provides a sealing layer that seals metal bonding structures between three dimensional bonded integrated circuits from a surrounding environment. A material may be applied to fill a volume between the bonded integrated circuits or seal the perimeter of the volume between the bonded integrated circuits. The material may be the same material as that used for underfilling the volume between the bottom integrated circuit and a substrate.Type: GrantFiled: March 1, 2004Date of Patent: May 15, 2007Assignee: Intel CorporationInventors: Patrick Morrow, Grant Kloster
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Patent number: 7176422Abstract: A heater for flip chip bonding transfers more heat to the periphery of a die than to the center. This may result in a more even temperature profile along the die and may help prevent epoxy voiding problems.Type: GrantFiled: June 17, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Song-Hua Shi
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Patent number: 7164206Abstract: The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is disposed above and on the diffusion barrier layer. The etch stop layer has a second thickness and a second dielectric constant.Type: GrantFiled: March 28, 2001Date of Patent: January 16, 2007Assignee: Intel CorporationInventors: Grant Kloster, Jihperng Leu, Lawrence Wong, Andrew Ott, Patrick Marrow
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Patent number: 7160779Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.Type: GrantFiled: February 23, 2005Date of Patent: January 9, 2007Assignee: Intel CorporationInventors: Mark L. Doczy, Jack Kavalieros, Justin K. Brask, Matthew V. Metz, Suman Datta, Brian S. Doyle, Robert S. Chau
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Patent number: 7141843Abstract: Embodiments of the invention provide a polarization rotator. The polarization rotator may be integrated with a waveguide on a substrate, and may include a ferromagnetic semiconductor layer on the substrate, a first doped layer on the ferromagnetic semiconductor layer, and a second doped layer on the first doped layer.Type: GrantFiled: October 11, 2004Date of Patent: November 28, 2006Assignee: Intel CorporationInventors: Michael S. Salib, Dmitri Nikonov
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Patent number: 7124931Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.Type: GrantFiled: November 18, 2003Date of Patent: October 24, 2006Assignee: Intel CorporationInventors: J. Shelton Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
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Patent number: 7112859Abstract: Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer layer.Type: GrantFiled: May 17, 2004Date of Patent: September 26, 2006Assignee: Intel CorporationInventors: Ibrahim Ban, Bernhard Sell, Sanjay Natarajan, Mark Bohr
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Patent number: 7105925Abstract: Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dimensions and uniformity of various layers may be accurately controlled using the disclosed techniques.Type: GrantFiled: February 2, 2005Date of Patent: September 12, 2006Assignee: Intel CorporationInventors: James A. Boardman, Sarah E. Kim, Paul B. Fischer, Mauro J. Kobrinsky
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Patent number: 7091560Abstract: Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.Type: GrantFiled: March 22, 2004Date of Patent: August 15, 2006Assignee: Intel CorporationInventors: Mark A. Stettler, Borna Obradovic, Martin D. Giles, Rafael Rios
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Patent number: 7071554Abstract: In some embodiments, the invention provides a stress mitigation layer that reduces stress in a layer of a microelectronic device that is below a conductive connection structure, such as a bump.Type: GrantFiled: May 27, 2004Date of Patent: July 4, 2006Assignee: Intel CorporationInventors: Makarem A. Hussein, Jun He
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Patent number: 7063268Abstract: Embodiments of the invention provide one or more valves in which an electroactive material acts to open or close the valves to increase efficiency of a pump, which may be a pump that uses an electroactive diaphragm to pump fluid. The valves and pump may pump fluid to cool a device in a system.Type: GrantFiled: June 21, 2004Date of Patent: June 20, 2006Assignee: Intel CorporationInventors: Gregory M. Chrysler, Gilroy J. Vandentop
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Patent number: 7061116Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.Type: GrantFiled: September 26, 2001Date of Patent: June 13, 2006Assignee: Intel CorporationInventors: Carolyn McCormick, Rebecca Jessep, John Dungan, David W. Boggs, Daryl Sato
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Patent number: 7049208Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.Type: GrantFiled: October 11, 2004Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Sriram Muthukumar, Devendra Natekar
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Patent number: 7045428Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer that has a second substantially vertical component, a second metal layer is formed on the second gate dielectric layer. In this method, a conductor is formed that contacts both the first metal layer and the second metal layer.Type: GrantFiled: May 26, 2004Date of Patent: May 16, 2006Assignee: Intel CorporationInventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Uday Shah, Chris E. Barns, Suman Datta, Robert B. Turkot, Jr., Robert S. Chau
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Patent number: 7045073Abstract: A method for anisotropically and selectively removing a dielectric thin film layer from a substrate layer is disclosed, wherein the dielectric layer is subjected to ion implantation prior to wet etching. This method may be applied adjacent to a structure such as a gate electrode within a microelectronic structure to prevent undercutting of the dielectric material to be preserved between the gate electrode and the substrate layer, as may happen with more isotropic etching techniques.Type: GrantFiled: December 18, 2002Date of Patent: May 16, 2006Assignee: Intel CorporationInventors: Scott A. Hareland, Nick Lindert, Reza Arghavani, Robert Chau
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Patent number: 7038207Abstract: Diffraction which is used to measure features on a substrate layer is disclosed. A substrate, such as a mask structure for microelectronics or a semiconductor substrate with reflective or transmissive features, is irradiated by a source emitting radiation of known wavelength at an angle of incidence relative to the substrate. Given a known pitch, the width of the features themselves is measured by analyzing a diffraction pattern by computer after capturing characteristics of the pattern with a detector.Type: GrantFiled: September 12, 2003Date of Patent: May 2, 2006Assignee: Intel CorporationInventor: David H. Hwang
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Patent number: 7018918Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.Type: GrantFiled: November 3, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Grant M. Kloster, Kevin P. O'brien, Michael D. Goodner, Jihperng Leu, David H. Gracias, Lee D. Rockford, Peter K. Moon, Chris E. Barns