Patents Represented by Attorney Michael D. Rostoker
  • Patent number: 5312770
    Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion 58 region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: May 17, 1994
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 5310455
    Abstract: A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: May 10, 1994
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Thomas G. Mallon, Mark A. Franklin
  • Patent number: 5307559
    Abstract: A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or conductive epoxy through cutouts in the pad. In one embodiment, the cutouts extend into the pad from inner and outer edges thereof. In another embodiment, the cutouts are holes through the pad. A plurality, such as four, capacitors are conveniently disposed atop a corresponding plurality of pads, and are connected to a corresponding plurality of pairs of leads within the semiconductor device assembly. By positioning the capacitor(s) as closely to the semiconductor device as possible, the efficacy of the capacitor(s) is maximized. Method and apparatus are disclosed.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: May 3, 1994
    Assignee: LSI Logic Corporation
    Inventor: Jon Long
  • Patent number: 5299730
    Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: April 5, 1994
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Vahak K. Sahakian, Conrad J. Dell'Oca
  • Patent number: 5298110
    Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: March 29, 1994
    Assignee: LSI Logic Corporation
    Inventors: Philippe Schoenborn, Nicholas F. Pasch
  • Patent number: 5290396
    Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: March 1, 1994
    Assignee: LSI Logic Corporation
    Inventors: Philippe Schoenborn, Nicholas F. Pasch
  • Patent number: 5287247
    Abstract: A computer system module includes a central processing unit (CPU), a floating-point accelerator (FPA), a read/write buffer (RWB), cache memory, a clock generator, buffers, and reset logic. The signal composition of the module includes: Configuration Buffer Enable (CfgEn); Page Write (PgWrt); Block Match (BlkMtch); Byte Write Mask (WrMsk); and Test Enable (TestEn). The layout of the various components on a printed circuit board (PCB) minimizes transmission line effects, such as transmission line delay (t.sub.D) and signal reflections, by keeping trace lengths as short as possible, and no line terminations are required. A heat sink (heat spreader) is provided for critical semiconductor devices, such as the CPU and the FPA. The heat sink includes a broad flat section and a button protruding from a surface thereof. An unpackaged device is mounted to the button, with a thermally and electrically conductive adhesive, and is inserted through a hole in the PCB.
    Type: Grant
    Filed: August 26, 1992
    Date of Patent: February 15, 1994
    Assignee: LSI Logic Corporation
    Inventors: Geard D. Smits, Leonardo Vainesencher
  • Patent number: 5286519
    Abstract: A fluid distribution head of this invention includes a chamber for fluid flow including a perforated plate. The perforated plate is internally supported by a structural support to avoid deformation of the plate.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: February 15, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael Vukelic
  • Patent number: 5284797
    Abstract: Bond pad lift problems encountered during bonding are alleviated by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad. Conductive material fills the at least one opening, and electrically connects the top and bottom bond pads. In one embodiment, the at least one opening is a plurality of conductive vias. In another embodiment, the at least one opening is a ring-like opening extending around the peripheral region. In yet another embodiment, the at least one opening is one or more elongated slit-like openings.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: February 8, 1994
    Assignee: LSI Logic Corporation
    Inventor: Dorothy A. Heim
  • Patent number: 5278769
    Abstract: An automatic logic-model generation system operates on a schematic database and produces logic models incorporating accurate timing information. A verification process is also performed whereby the model is automatically verified for accuracy.
    Type: Grant
    Filed: April 12, 1991
    Date of Patent: January 11, 1994
    Assignee: LSI Logic Corporation
    Inventors: Owen S. Bair, Patrick Yin, Chih-Chung Chen
  • Patent number: 5278447
    Abstract: Damage to the package body and external leads of a leaded semiconductor device assembly is prevented by a carrier assembly. The carrier assembly includes a rigid bottom (lower) plate positively supporting the package body and providing a bottom cover for the external leads. A semi-rigid top (upper) plate positively holds the package body against the bottom plate, prevents movement of the package body with respect to the carrier assembly, and covers the external leads. Fasteners are provided for securing the upper plate to the lower plate, preferably at the four corners of the plates. In this manner, a durable "sandwich" structure is created, with the package disposed between the lower and upper plates and the body and leads well protected against damage.
    Type: Grant
    Filed: January 16, 1992
    Date of Patent: January 11, 1994
    Assignee: LSI Logic Corporation
    Inventors: Sutee Vongfuangfoo, Matthew Preston
  • Patent number: 5275326
    Abstract: Damage to the pins and ceramic body of pin grid array type semiconductor device assemblies is avoided by providing ceramic bushings in the pin-receiving holes of a boat transport. The bushings elevate the package body above the platform surface of the boat, and also alleviate problems associated with unequal thermal expansion of the metal boat and the ceramic package. In an alternate embodiment, a ceramic insert formed as a square ring encompassing an area roughly equivalent to the area of the package body is provided with holes for receiving the pins, and the boat transport has a cavity for receiving and retaining the ceramic insert.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: January 4, 1994
    Assignee: LSI Logic Corporation
    Inventor: Wallace A. Fiedler
  • Patent number: 5262927
    Abstract: A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a square ring, having an opening containing a heat sink element. A lower PCB is also formed as a square ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package.
    Type: Grant
    Filed: February 7, 1992
    Date of Patent: November 16, 1993
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim
  • Patent number: 5260514
    Abstract: A fully-populated Pin Grid Array (PGA) is vacuum-chucked to a pedestal, without mechanical clamping. The pedestal includes a cylindrical shaft having a vacuum passageway extending its length, and a vacuum reservoir block mounted atop the shaft, and an alignment/fixture plate mounted atop the vacuum reservoir block. The alignment/fixture plate is provided with holes extending partially through the plate, at least about its periphery, for receiving the outermost rows/columns of pins of the PGA, while maintaining a vacuum seal. In one embodiment, a central portion of the alignment/fixture plate is provided with a large through-opening for receiving the remaining pins of the PGA. In another embodiment, the central portion of the alignment/fixture plate is provided with a plurality of individual through holes corresponding to the remaining pins of the PGA. In this manner, the PGA is held securely and well aligned within a wire bonder, while avoiding damaging the pins.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: November 9, 1993
    Assignee: LSI Logic Corporation
    Inventor: William J. Fruen, Jr.
  • Patent number: 5254940
    Abstract: A technique of gaining direct access to the inputs and outputs of an embedded microprocessor, otherwise buried behind additional logic, is disclosed. Multiplexers are provided for at least the embedded microprocessor inputs and outputs. In a test mode, the multiplexers connect device input and output pads directly to the embedded microprocessor inputs and outputs. In a normal operating mode, the multiplexers connect the additional logic to the input and output pads. Preferably, in order to standardize design criteria, multiplexers are provided on all of the inputs and outputs of the microprocessor which may become embedded behind additional logic. Additionally, it is possible in the test mode to control the additional logic to a well defined state. The invention provides a simple way to isolate the embedded microprocessor from the rest of the logic and test it thoroughly using test vectors that have already been developed for the stand-alone microprocessor.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: October 19, 1993
    Assignee: LSI Logic Corporation
    Inventors: Timothy P. Oke, Russell E. Cummings, II, Nachum M. Gavrielov
  • Patent number: 5248625
    Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.
    Type: Grant
    Filed: August 22, 1991
    Date of Patent: September 28, 1993
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 5249281
    Abstract: A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: September 28, 1993
    Assignee: LSI Logic Corporation
    Inventors: Michael Fuccio, Sanjay Desai
  • Patent number: 5248903
    Abstract: Bond pad lift problems encountered during bonding are alleviated by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad. Conductive material fills the at least one opening, and electrically connects the top and bottom bond pads. In one embodiment, the at least one opening is a plurality of conductive vias. In another embodiment, the at least one opening is a ring-like opening extending around the peripheral region. In yet another embodiment, the at least one opening is one or more elongated slit-like openings.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: September 28, 1993
    Assignee: LSI Logic Corporation
    Inventor: Dorothy A. Heim
  • Patent number: 5247153
    Abstract: The surface of an optical element, such as the taking lens in semiconductor photolithographic apparatus, is deformed, in situ, by applying heat to the surface. A recipe for applying the heat to a selected area of the lens surface is developed by either measuring the image projected by the lens and comparing the measured image to the specified (mask) image, or by measuring the contour of the surface of the lens and comparing the measured contour to the lens' specified contour. The heat is applied by a laser, the output of which is focussed and scanned onto the surface of the lens. Method and apparatus are disclosed.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: September 21, 1993
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 5245790
    Abstract: A technique for chemi-mechanical polishing of semiconductor wafers using ultrasonic energy is disclosed. A transducer is mounted in the polishing system, either to a platen to which the polishing pad is mounted, or to a carrier to which the semiconductor wafer is mounted. In either case, relative vibratory motion is established between the wafer and the polishing pad. The transducer may also be mounted within the reservoir containing the platen, carrier and polishing slurry, to agitate the slurry itself. By vibrating the polishing pad relative to the wafer, polish rate and repeatability are enhanced, the polishing process is less sensitive to pad use history, and the pad is somewhat self-conditioning.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: September 21, 1993
    Assignee: LSI Logic Corporation
    Inventor: Chris Jerbic