Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
Type:
Grant
Filed:
July 16, 2008
Date of Patent:
July 20, 2010
Assignee:
Xilinx, Inc.
Inventors:
Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele, Suresh M. Menon