Abstract: Reducing or eliminating watermark-type defects during semiconductor device fabrication are described and can comprise treating photoresist using one of several embodiments. In some embodiments, the propensity for defect formation is reduced/eliminated by conditioning the photoresist surface through the application and removal of a sacrificial overcoat. In other embodiments, existing defects are reduced/eliminated by exposing the photoresist surface to a defect-stripping material during post-develop processing.
Type:
Grant
Filed:
March 10, 2008
Date of Patent:
April 24, 2012
Assignee:
Micron Technology, Inc.
Inventors:
Yoshiki Hishiro, Lijing Gou, Scott E. Sills, Hiroyuki Mori, Paul D. Shirley, Troy V. Gugel, Adam L. Olson
Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
Type:
Grant
Filed:
October 5, 2006
Date of Patent:
March 6, 2012
Assignee:
Micron Technology, Inc.
Inventors:
John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
Abstract: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.
Abstract: Via structures are described which pass through a semiconductor substrate assembly such as a semiconductor die or wafer and allows for two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other connection electrically connects to a conductive pad. To connect to a pad, a larger opening is etched into an overlying dielectric layer, while to pass through a pad without connection, a narrower opening is etched into the overlying dielectric layer.
Abstract: A storage container having a storage tub and lid is described. The lid can be opened for access to an interior region of the tub. A solid-state light source or electro-luminescence is located to illuminate the interior region of the tub in response to an actuated switch contained within the lid. The switch can be gravity actuated. The solid-state light source can emit visible or ultraviolet light wavelengths.
Type:
Grant
Filed:
August 6, 2004
Date of Patent:
July 25, 2006
Inventors:
Daniel H. Fitzsimmons, Molly M Fitzsimmons